IP Library Granted Patent US 7,855,378
Granted Patent B2
US 7,855,378 · App. 11/836,093 · Granted Dec 21, 2010

Phase change memory devices and methods for fabricating the same

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Quick Facts
Patent No.
US 7,855,378
App. No.
11/836,093
Granted
Dec 21, 2010
Kind
B2
Abstract

Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and partially protrudes over the first dielectric layer, wherein the heating electrode includes an intrinsic portion embedded within the first dielectric layer, a reduced portion stacked over the intrinsic portion, and an oxide spacer surrounding a sidewall of the reduced portion. A phase change material layer is formed over the first dielectric layer and covers the heating electrode, the phase change material layer contacts a top surface of the reduced portion of the heating electrode. A top electrode is formed over the phase change material layer and contacts the phase change material layer.

Claims (15)

1. A phase change memory device, comprising:

a bottom electrode formed over a substrate;

a first dielectric layer formed over the bottom electrode;

a heating electrode formed in the first dielectric layer, partially protruding over the first dielectric layer, wherein the heating electrode comprising:

an intrinsic portion having a first diameter embedded within the first dielectric layer;

a reduced portion having a second diameter less than the first diameter stacked over the intrinsic portion, wherein the second diameter of the reduced portion is uniform from a top surface to a bottom surface thereof; and

an oxide spacer surrounding a sidewall of the reduced portion stacked over the intrinsic portion;

a phase change material layer formed over the first dielectric layer, covering the heating electrode, wherein the phase change material layer contacts the top surface of the reduced portion of the heating electrode and surrounds a sidewall surface of the oxide spacer and physically contacts the first dielectric layer; and

a top electrode formed over the phase change material layer, contacting the phase change material layer.

2. The phase change memory device as claimed in claim 1 , wherein the second diameter of the reduced portion of the heating electrode is about 5˜1000 Å.

3. The phase change memory device as claimed in claim 1 , wherein the reduced portion of the heating electrode is substantially stacked over the intrinsic portion of the heating electrode along an axial direction.

4. The phase change memory device as claimed in claim 1 , wherein the reduced portion of the heating electrode and the phase change material layer are isolated by the oxide spacer.

5. The phase change memory device as claimed in claim 1 , wherein a bottom surface of the reduced portion of the heating electrode is slightly lower than a top surface of the first dielectric layer.

6. The phase change memory device as claimed in claim 1 , further comprising a second dielectric layer formed over the first dielectric layer, surrounding a sidewall of the phase change material layer, wherein the top electrode is partially formed over the second dielectric layer.

7. The phase change memory device as claimed in claim 1 , wherein the phase change material layer comprises chalcogenide materials.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2019
From: POWERCHIP TECHNOLOGY CORPORATION
To: POWERCHIP SEMICONDUCTOR MANUFACTURING CORPORATION
Reel/Frame 049770/0090 →
CHANGE OF NAME Recorded Jun 26, 2019
From: POWERCHIP SEMICONDUCTOR CORP.
To: POWERCHIP TECHNOLOGY CORPORATION
Reel/Frame 049602/0564 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 28, 2010
From: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE; NANYA TECHNOLOGY CORPORATION; PROMOS TECHNOLOGIES INC.; WINBOND ELECTRONICS CORP.
To: POWERCHIP SEMICONDUCTOR CORP.
Reel/Frame 024149/0097 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2007
From: LIN, YUNG-FA; WANG, TE-CHUN
To: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE; POWERCHIP SEMICONDUCTOR CORP.; NANYA TECHNOLOGY CORPORATION; PROMOS TECHNOLOGIES INC.; WINBOND ELECTRONICS CORP.
Reel/Frame 019697/0298 →