Metal oxide semiconductor transistor
View Patent ↗The present invention provides a method for fabricating a metal oxide semiconductor transistor. First, a semiconductor substrate is provided and at least a gate is formed on the semiconductor substrate. A protective layer is then formed on the semiconductor substrate and the gate. Subsequently, at least a recess is formed in the semiconductor substrate adjacent to the gate, and then an epitaxial layer is formed in the recess. A lightly doped region is formed in the semiconductor substrate adjacent to the gate. Finally, a spacer is formed on the sidewall of the gate.
1. A MOS transistor structure, comprising:
a gate formed on a semiconductor substrate;
two raised epitaxial layers positioned respectively in the semiconductor substrate next to the relative sides of the gate and above the surface of the semiconductor substrate;
a spacer formed on the sidewall of the gate and extending laterally upon a portion of the raised epitaxial layers, and a contact surface of the raised epitaxial layers and a bottom of the spacer is above the surface of the semiconductor substrate; and
two doped region formed respectively in the semiconductor substrate next to the relative sides of the gate.
2. The structure of claim 1 , wherein the gate further comprises:
a dielectric layer;
a conductive layer, positioned on the dielectric layer; and
a cap layer, positioned on the conductive layer.
3. The structure of claim 1 , wherein the MOS transistor comprises a PMOS transistor.
4. The structure of claim 3 , wherein the epitaxial layer comprises SiGe.
5. The structure of claim 1 , wherein the MOS transistor comprises an NMOS transistor.
6. The structure of claim 5 , wherein the epitaxial layer comprises SiC.
7. The structure of claim 1 , wherein the spacer further comprises an offset spacer, positioned between the gate and the spacer.
8. The structure of claim 1 , wherein the spacer further comprises an oxide liner and a nitride spacer.
9. The structure of claim 1 , wherein the edge of the raised epitaxial layers is not aligned with the edge of the spacer.
10. The structure of claim 1 , wherein the spacer further comprises a L-shaped spacer.
11. The structure of claim 1 , further comprising a lightly doped drain disposed in the semiconductor substrate and outside the raised epitaxial layers.