Top layers of metal for high performance IC's
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
1 . An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple devices, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure comprises electroplated copper;
a second dielectric layer between said first and second metal layers;
a passivation layer over said metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a contact point of said metallization structure; and
a metal contact over said contact point, wherein said metal contact comprises nickel and copper.
2 . The integrated circuit chip of claim 1 further comprising a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said contact point.
3 . The integrated circuit chip of claim 2 , wherein said polymer layer comprises polyimide.
4 . The integrated circuit chip of claim 2 , wherein said polymer layer comprises benzocyclobutene (BCB).
5 . The integrated circuit chip of claim 2 , wherein said polymer layer has a thickness between 2 and 30 microns.
6 . The integrated circuit chip of claim 1 further comprising a solder bump connected to said contact point through said metal contact.
7 . The integrated circuit chip of claim 1 further comprising a wirebonding interconnect pad connected to said contact point through said metal contact.
8 . The integrated circuit chip of claim 1 , wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip.
9 . The integrated circuit chip of claim 1 , wherein said passivation layer comprises a nitride layer having a thickness between 0.5 and 2 microns.
10 . The integrated circuit chip of claim 1 , wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer.
11 . An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a contact point of said first metallization structure; and
a second metallization structure connected to said contact point through said first opening, wherein said second metallization structure comprises nickel and copper.
12 . The integrated circuit chip of claim 11 further comprising a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said contact point.
13 . The integrated circuit chip of claim 12 , wherein said polymer layer comprises polyimide.
14 . The integrated circuit chip of claim 12 , wherein said polymer layer comprises benzocyclobutene (BCB).
15 . The integrated circuit chip of claim 12 , wherein said polymer layer has a thickness between 2 and 30 microns.
16 . The integrated circuit chip of claim 11 further comprising a solder bump connected to said contact point through said second metallization structure.
17 . The integrated circuit chip of claim 11 , wherein said second metallization structure comprises a wirebonding interconnect pad connected to said contact point through said first opening.
18 . The integrated circuit chip of claim 11 , wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip.
19 . The integrated circuit chip of claim 11 , wherein said passivation layer comprises a nitride layer having a thickness between 0.5 and 2 microns.
20 . The integrated circuit chip of claim 11 , wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer.