IP Library Patent Application 11839560
Patent Application
App. No. 11/839,560

Top layers of metal for high performance IC's

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Patent No.
US None
App. No.
11/839,560
Abstract

A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.

Claims (41)

1 . An integrated circuit chip comprising:

a silicon substrate;

multiple devices in and on said silicon substrate;

a first dielectric layer over said silicon substrate;

a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper;

a second dielectric layer between said first and second metal layers;

a passivation layer over said first metallization structure, a first opening in said passivation layer exposing a contact point of said first metallization structure, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and

a second metallization structure comprising a wirebonding interconnect pad connected to said contact point through said first opening, wherein said second metallization structure comprises a tungsten-containing metal structure and an electroplated metal structure over said tungsten-containing metal structure.

2 . The integrated circuit chip of claim 1 , wherein said electroplated metal structure comprises copper.

3 . The integrated circuit chip of claim 1 further comprising a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said contact point.

4 . The integrated circuit chip of claim 3 , wherein said polymer layer comprises polyimide.

5 . The integrated circuit chip of claim 3 , wherein said polymer layer comprises benzocyclobutene (BCB).

6 . The integrated circuit chip of claim 3 , wherein said polymer layer has a thickness between 2 and 30 microns.

7 . An integrated circuit chip comprising:

a silicon substrate;

multiple devices in and on said silicon substrate;

a first dielectric layer over said silicon substrate;

a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper;

a second dielectric layer between said first and second metal layers;

a passivation layer over said first metallization structure, a first opening in said passivation layer exposing a contact point of said first metallization structure, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and

a second metallization structure comprising a wirebonding interconnect pad connected to said contact point through said first opening, wherein said second metallization structure comprises a sputtered metal structure and an electroplated metal structure over said sputtered metal structure.

8 . The integrated circuit chip of claim 7 , wherein said electroplated metal structure comprises copper.

9 . The integrated circuit chip of claim 7 , wherein said sputtered metal structure comprises aluminum.

10 . The integrated circuit chip of claim 7 further comprising a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said contact point.

11 . The integrated circuit chip of claim 10 , wherein said polymer layer comprises polyimide.

12 . The integrated circuit chip of claim 10 , wherein said polymer layer comprises benzocyclobutene (BCB).

13 . The integrated circuit chip of claim 10 , wherein said polymer layer has a thickness between 2 and 30 microns.

14 . An integrated circuit chip comprising:

a silicon substrate;

multiple devices in and on said silicon substrate;

a first dielectric layer over said silicon substrate;

a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper;

a second dielectric layer between said first and second metal layers;

a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a contact point of said first metallization structure, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and

a second metallization structure comprising a wirebonding interconnect pad connected to said contact point through said first opening, wherein said second metallization structure comprises electroplated copper.

15 . The integrated circuit chip of claim 14 further comprising a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said contact point.

16 . The integrated circuit chip of claim 15 , wherein said polymer layer has a thickness between 2 and 30 microns.

17 . The integrated circuit chip of claim 15 , wherein said polymer layer comprises polyimide.

18 . The integrated circuit chip of claim 15 , wherein said polymer layer comprises benzocyclobutene (BCB).

19 . The integrated circuit chip of claim 14 , wherein said second metallization structure further comprises aluminum.

20 . The integrated circuit chip of claim 14 , wherein said second metallization structure further comprises nickel.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2014
From: MEGIT ACQUISITION CORP.
To: QUALCOMM INCORPORATED
Reel/Frame 033303/0124 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 20, 2009
From: LIN, MOU-SHIUNG, DR.
To: MEGICA CORPORATION
Reel/Frame 023119/0387 →