Top layers of metal for high performance IC's
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
1 . An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises a contact point comprising electroplated copper;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing said contact point, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and
a second metallization structure over said passivation layer and over said contact point, comprising a metal contact over said contact point and an electroplated metal structure connected to said contact point through said metal contact, wherein said metal contact comprises aluminum.
2 . The integrated circuit chip of claim 1 further comprising a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said contact point.
3 . The integrated circuit chip of claim 2 , wherein said polymer layer has a thickness between 2 and 30 microns.
4 . The integrated circuit chip of claim 2 , wherein said polymer layer comprises polyimide.
5 . The integrated circuit chip of claim 2 , wherein said polymer layer comprises benzocyclobutene (BCB).
6 . The integrated circuit chip of claim 1 , wherein said electroplated metal structure comprises copper.
7 . The integrated circuit chip of claim 1 , wherein said topmost nitride layer has a thickness between 0.5 and 2 microns.
8 . An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises a contact point comprising electroplated copper;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing said contact point;
a polymer layer over said passivation layer, a second opening in said polymer layer exposing said contact point, wherein said polymer layer has a thickness of greater than 2 microns; and
a second metallization structure over said passivation layer, over said polymer layer and over said contact point, wherein said second metallization structure comprises aluminum.
9 . The integrated circuit chip of claim 8 , wherein said thickness is between 2 and 30 microns.
10 . The integrated circuit chip of claim 8 , wherein said polymer layer comprises polyimide.
11 . The integrated circuit chip of claim 8 , wherein said polymer layer comprises benzocyclobutene (BCB).
12 . The integrated circuit chip of claim 8 , wherein said second metallization structure further comprises copper.
13 . The integrated circuit chip of claim 8 , wherein said second metallization structure further comprises nickel.
14 . The integrated circuit chip of claim 8 , wherein said second metallization structure further comprises tungsten.
15 . The integrated circuit chip of claim 8 , wherein said second metallization structure further comprises chromium.
16 . The integrated circuit chip of claim 8 , wherein said second metallization structure further comprises an electroplated metal.
17 . The integrated circuit chip of claim 8 , wherein said second metallization structure further comprises an electroless metal.
18 . The integrated circuit chip of claim 8 , wherein said second metallization structure further comprises a sputtered metal.
19 . The integrated circuit chip of claim 8 , wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip.
20 . The integrated circuit chip of claim 8 , wherein said passivation layer comprises a nitride layer having a thickness between 0.5 and 2 microns.