Top layers of metal for high performance IC's
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
1 . An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises electroplated copper, and wherein said metallization structure comprises a first pad and a second pad neighboring to said first pad;
a second dielectric layer between said first and second metal layers;
a passivation layer over said metallization structure and over said first and second dielectric layers, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip;
a first wiring over said passivation layer;
a second wiring over said passivation layer;
a first rerouted pad connected to said first pad through said first wiring; and
a second rerouted pad connected to said second pad through said second wiring, wherein the distance between said first and second rerouted pads is greater than that between said first and second pads.
2 . The integrated circuit chip of claim 1 , wherein said first wiring comprises electroplated copper.
3 . The integrated circuit chip of claim 1 , wherein said first wiring comprises aluminum.
4 . The integrated circuit chip of claim 1 , wherein said first wiring comprises nickel.
5 . The integrated circuit chip of claim 1 further comprising a polymer layer between said first wiring and said passivation layer and between said second wiring and said passivation layer.
6 . The integrated circuit chip of claim 5 , wherein said polymer layer has a thickness between 2 and 30 microns.
7 . The integrated circuit chip of claim 5 , wherein said polymer layer comprises polyimide.
8 . The integrated circuit chip of claim 5 , wherein said polymer layer comprises benzocyclobutene (BCB).
9 . An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises electroplated copper;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said first metallization structure, a second opening in said passivation layer exposing a second pad of said first metallization structure, and a third opening in said passivation layer exposing a third pad of said first metallization structure, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and
a second metallization structure over said passivation layer and over said first, second and third pads, wherein said second metallization structure comprises a fourth pad connected to said first, second and third pads through said first, second and third openings.
10 . The integrated circuit chip of claim 9 , wherein said second metallization structure comprises electroplated copper.
11 . The integrated circuit chip of claim 9 , wherein said second metallization structure comprises aluminum.
12 . The integrated circuit chip of claim 9 , wherein said second metallization structure comprises nickel.
13 . The integrated circuit chip of claim 9 further comprising a polymer layer on said passivation layer, wherein a fourth opening in said polymer layer is over said first pad, a fifth opening in said polymer layer is over said second pad, and a sixth opening in said polymer layer is over said third pad, and wherein said second metallization structure is over said polymer layer.
14 . The integrated circuit chip of claim 13 , wherein said polymer layer has a thickness between 2 and 30 microns.
15 . The integrated circuit chip of claim 13 , wherein said polymer layer comprises polyimide.
16 . The integrated circuit chip of claim 13 , wherein said polymer layer comprises benzocyclobutene (BCB).
17 . The integrated circuit chip of claim 9 further comprising a solder bump over said fourth pad.
18 . The integrated circuit chip of claim 9 , wherein said fourth pad is applicable to wirebonding for making further circuit connects.
19 . An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, multiple openings in said passivation layer exposing multiple first pads of said first metallization structure, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and
a second metallization structure over said passivation layer and over said multiple first pads, wherein the number of multiple second pads of said second metallization structure is larger than that of said multiple first pads, and wherein said second pads are applicable to wirebonding for making further circuit connects.
20 . The integrated circuit chip of claim 19 , wherein said second metallization structure comprises electroplated copper.
21 . The integrated circuit chip of claim 19 , wherein said second metallization structure comprises aluminum.
22 . The integrated circuit chip of claim 19 , wherein said second metallization structure comprises nickel.