Top layers of metal for high performance IC's
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
1 . A method for fabricating an integrated circuit chip comprising:
providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first metallization structure over said first dielectric layer and connected to said multiple devices, said first metallization structure comprising a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, and a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a contact point of said first metallization structure, wherein said first metallization structure comprises electroplated copper, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and
forming a second metallization structure over said passivation layer and over said contact point, wherein said second metallization structure comprises a first metal structure and a second metal structure over said first metal structure, wherein said first metal structure is formed by a first process comprising sputtering, and said second metal structure is formed by a second process comprising electroplating.
2 . The method of claim 1 , wherein said first process comprises sputtering aluminum.
3 . The method of claim 1 , wherein said second process comprises electroplating copper.
4 . The method of claim 1 further comprising forming a solder bump over said second metal structure.
5 . The method of claim 1 , wherein said forming said second metallization structure comprises forming a wirebonding interconnect pad connected to said contact point.
6 . The method of claim 1 further comprising providing a polymer layer on said passivation layer, a second opening in said polymer layer exposing said contact point, followed by said forming said second metallization structure over said polymer layer.
7 . The method of claim 6 , wherein said providing said polymer layer comprises forming said polymer layer on said passivation layer using a process comprising coating and curing.
8 . The method of claim 6 , wherein said providing said polymer layer comprises forming a photosensitive polyimide on said passivation layer.
9 . A method for fabricating an integrated circuit chip comprising:
providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first metallization structure over said first dielectric layer and connected to said multiple devices, said first metallization structure comprising a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, and a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a contact point of said first metallization structure, wherein said first metallization structure comprises electroplated copper, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and
forming a second metallization structure over said passivation layer and over said contact point, wherein said second metallization structure comprises a first metal structure and a second metal structure over said first metal structure, wherein said first metal structure is formed by a first process comprising electroplating, and said second metal structure is formed by a second process comprising electroplating.
10 . The method of claim 9 , wherein said first process comprises electroplating copper.
11 . The method of claim 9 , wherein said second process comprises electroplating copper.
12 . The method of claim 9 further comprising forming a solder bump over said second metal structure.
13 . The method of claim 9 , wherein said forming said second metallization structure comprises forming a wirebonding interconnect pad connected to said contact point.
14 . The method of claim 9 further comprising providing a polymer layer on said passivation layer, a second opening in said polymer layer exposing said contact point, followed by said forming said second metallization structure over said polymer layer.
15 . A method for fabricating an integrated circuit chip comprising:
providing a silicon substrate, multiple devices in and on said silicon substrate, a first dielectric layer over said silicon substrate, a first metallization structure over said first dielectric layer and connected to said multiple devices, said first metallization structure comprising a first metal layer and a second metal layer over said first metal layer, a second dielectric layer between said first and second metal layers, and a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a contact point of said first metallization structure, wherein said first metallization structure comprises electroplated copper, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and
forming a second metallization structure over said passivation layer and over said contact point, wherein said second metallization structure comprises a first metal structure and a second metal structure over said first metal structure, wherein said first metal structure is formed by a first process comprising electroless plating, and said second metal structure is formed by a second process comprising electroplating.
16 . The method of claim 15 , wherein said first process comprises electroless plating nickel.
17 . The method of claim 15 , wherein said second process comprises electroplating copper.
18 . The method of claim 15 further comprising forming a solder bump over said second metal structure.
19 . The method of claim 15 , wherein said forming said second metallization structure comprises forming a wirebonding interconnect pad connected to said contact point.
20 . The method of claim 15 further comprising providing a polymer layer on said passivation layer, a second opening in said polymer layer exposing said contact point, followed by said forming said second metallization structure over said polymer layer.