Apparatus and method for controlled particle beam manufacturing
A chamber for exposing a workpiece to charged particles includes a charged particle source for generating a stream of charged particles, a collimator configured to collimate and direct the stream of charged particles from the charged particle source along an axis, a beam digitizer downstream of the collimator configured to create a digital beam including groups of at least one charged particle by adjusting longitudinal spacing between the charged particles along the axis, a deflector downstream of the beam digitizer including a series of deflection stages disposed longitudinally along the axis to deflect the digital beams, and a workpiece stage downstream of the deflector configured to hold the workpiece.
1. A method of fabricating a radiation hardened transistor, the method comprising:
exposing portions of a workpiece to a digital beam comprising temporally and spatially resolved digital flashes, each said digital flash comprising at least one particle, thereby implanting said particles into the workpiece; and
during exposing, varying potential energies of the flashes across a region of the workpiece.
2. The method of claim 1 , wherein the transistor comprises a silicon transistor.
3. The method of claim 1 , wherein varying the potential energies comprises varying the potential energies between about 5 and 500 keV.
4. The method of claim 1 , wherein varying the potential energies comprises varying the potential energies between about 5 and 200 keV.
5. The method of claim 1 , wherein at least some of the digital flashes include a single species.
6. The method of claim 1 , wherein at least some of the digital flashes include a plurality of species.
7. The method of claim 1 , wherein the region comprises a drain of the transistor.
8. The method of claim 1 , comprising exposing a first portion of the workpiece to the flashes to form a shallow junction at a channel edge, then varying the potential energies of the flashes and exposing a second portion of the workpiece to the varied flashes to form a deep junction under a contact.
9. The method of claim 1 , wherein the exposed region comprises a lightly doped drain including said particles at a plurality of depths.
10. The method of claim 1 , wherein varying the potential energies comprises forming a guard ring barrier by increasing potential energies of the flashes in areas of the workpiece comprising thicker oxide.
11. A radiation hardened transistor manufactured by the method of claim 1 .
12. A method of fabricating a radiation hardened transistor, the method comprising:
exposing portions of a workpiece to a digital beam comprising temporally and spatially resolved digital flashes, each said digital flash comprising at least one particle, thereby implanting said particles into the workpiece; and
during exposing, varying doses of the flashes across a region of the workpiece.
13. The method of claim 12 , wherein the transistor comprises a silicon transistor.
14. The method of claim 12 , wherein varying the doses comprises varying the doses between about 1×10 10 charged particles/cm 2 and 1×10 17 charged particles/cm 2 .
15. The method of claim 12 , wherein at least some of the digital flashes include a single species.
16. The method of claim 12 , wherein at least some of the digital flashes include a plurality of species.
17. The method of claim 12 , comprising exposing a first portion of the workpiece to the flashes to form a shallow junction at a channel edge, then varying the doses of the flashes and exposing a second portion of the workpiece to the varied flashes to form a deep junction under a contact.
18. The method of claim 12 , wherein the exposed region comprises a lightly doped drain including said particles at a plurality of depths.
19. The method of claim 12 , wherein varying the doses comprises forming a guard ring barrier by increasing doses of the flashes in areas of the workpiece comprising thicker oxide.
20. The method of claim 12 , wherein exposing the workpiece comprises forming lateral amorphous isolation barriers between a plurality of transistors on the workpiece.
21. The method of claim 20 , wherein the transistors comprise p-type transistors.
22. A radiation hardened transistor manufactured by the method of claim 12 .