Top layers of metal for high performance IC's
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
1 . An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a contact point of said first metallization structure, wherein said first opening has a transverse dimension between 0.5 and 3 microns, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and
a second metallization structure over said passivation layer and over said contact point, wherein said second metallization structure comprises a wirebonding interconnect pad connected to said contact point through said first opening.
2 . The integrated circuit chip of claim 1 further comprising a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said contact point, and wherein said second metallization structure is over said polymer layer.
3 . The integrated circuit chip of claim 2 , wherein said polymer layer has a thickness between 2 and 30 microns.
4 . The integrated circuit chip of claim 2 , wherein said polymer layer comprises polyimide.
5 . The integrated circuit chip of claim 2 , wherein said polymer layer comprises benzocyclobutene (BCB).
6 . The integrated circuit chip of claim 1 , wherein said second metallization structure comprises electroplated copper.
7 . The integrated circuit chip of claim 1 , wherein said second metallization structure comprises aluminum.
8 . The integrated circuit chip of claim 1 , wherein said second metallization structure comprises nickel.
9 . The integrated circuit chip of claim 1 , wherein said contact point comprises electroplated copper.
10 . The integrated circuit chip of claim 1 , wherein said contact point comprises aluminum.
11 . An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, and wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said first metallization structure, wherein said first opening has a transverse dimension between 0.5 and 3 microns, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip;
a second metallization structure over said passivation layer and over said first pad, wherein said second metallization structure comprises a second pad connected to said first pad through said first opening; and
a metal bump over said second pad.
12 . The integrated circuit chip of claim 11 further comprising a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said first pad, and wherein said second metallization structure is over said polymer layer.
13 . The integrated circuit chip of claim 12 , wherein said polymer layer has a thickness between 2 and 30 microns.
14 . The integrated circuit chip of claim 12 , wherein said polymer layer comprises polyimide.
15 . The integrated circuit chip of claim 12 , wherein said polymer layer comprises benzocyclobutene (BCB).
16 . The integrated circuit chip of claim 11 , wherein said second metallization structure comprises electroplated copper.
17 . The integrated circuit chip of claim 11 , wherein said second metallization structure comprises aluminum.
18 . The integrated circuit chip of claim 11 , wherein said second metallization structure comprises nickel.
19 . The integrated circuit chip of claim 11 , wherein said first metallization structure comprises electroplated copper.
20 . The integrated circuit chip of claim 11 , wherein said first metallization structure comprises aluminum.
21 . The integrated circuit chip of claim 11 , wherein said metal bump comprises solder.
22 . An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure is connected to said multiple devices, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises a contact point having a size between 0.3 and 5.0 microns;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing said contact point, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip; and
a second metallization structure over said passivation layer and over said contact point, wherein said second metallization structure comprises a wirebonding interconnect pad connected to said contact point through said first opening.
23 . The integrated circuit chip of claim 22 further comprising a polymer layer on said passivation layer, wherein a second opening in said polymer layer is over said contact point, and wherein said second metallization structure is over said polymer layer.
24 . The integrated circuit chip of claim 23 , wherein said polymer layer has a thickness between 2 and 30 microns.
25 . The integrated circuit chip of claim 23 , wherein said polymer layer comprises polyimide.
26 . The integrated circuit chip of claim 23 , wherein said polymer layer comprises benzocyclobutene (BCB).
27 . The integrated circuit chip of claim 22 , wherein said second metallization structure comprises electroplated copper.
28 . The integrated circuit chip of claim 22 , wherein said second metallization structure comprises aluminum.
29 . The integrated circuit chip of claim 22 , wherein said second metallization structure comprises nickel.
30 . The integrated circuit chip of claim 22 , wherein said contact point comprises electroplated copper.
31 . The integrated circuit chip of claim 22 , wherein said contact point comprises aluminum.