Top layers of metal for high performance IC's
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
1 . An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple devices, and wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a second dielectric layer between said first and second metal layers;
a passivation layer over said metallization structure and over said first and second dielectric layers, an opening in said passivation layer exposing a pad of said metallization structure;
a polymer layer over said passivation layer, wherein said polymer layer has a thickness of between 2 and 30 microns; and
a metal post in said polymer layer, wherein said metal post is connected to said pad through said opening, said metal post having a height greater than a transverse dimension of said metal post, and said polymer layer uncovering a top surface of said metal post.
2 . The integrated circuit chip of claim 1 , wherein said polymer layer comprises polyimide.
3 . The integrated circuit chip of claim 1 , wherein said polymer layer comprises benzocyclobutene (BCB).
4 . The integrated circuit chip of claim 1 , wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip.
5 . The integrated circuit chip of claim 1 , wherein said metal post comprises electroplated copper.
6 . The integrated circuit chip of claim 1 , wherein said metal post comprises an electroplated metal.
7 . The integrated circuit chip of claim 1 , wherein said metal post comprises nickel.
8 . The integrated circuit chip of claim 1 , wherein said metallization structure comprises electroplated copper.
9 . The integrated circuit chip of claim 1 , wherein said metallization structure comprises aluminum.
10 . The integrated circuit chip of claim 1 further comprising a solder bump over said top surface.
11 . The integrated circuit chip of claim 1 further comprising a metal interconnect on said polymer layer and on said top surface.
12 . The integrated circuit chip of claim 11 , wherein said metal interconnect comprises an electroplated metal.
13 . The integrated circuit chip of claim 11 , wherein said metal interconnect comprises electroplated copper.
14 . The integrated circuit chip of claim 1 further comprising a wirebonding interconnect pad connected to said metal post.
15 . An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a metallization structure over said first dielectric layer, wherein said metallization structure is connected to said multiple devices, and wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;
a second dielectric layer between said first and second metal layers;
a passivation layer over said metallization structure and over said first and second dielectric layers, an opening in said passivation layer exposing a pad of said metallization structure;
a polymer layer over said passivation layer, wherein said polymer layer has a thickness of between 2 and 30 microns; and
a metal post in said polymer layer, wherein said metal post is connected to said pad through said opening, said metal post having a height greater than a diameter of said metal post, and said polymer layer uncovering a top surface of said metal post.
16 . The integrated circuit chip of claim 15 , wherein said polymer layer comprises polyimide.
17 . The integrated circuit chip of claim 15 , wherein said polymer layer comprises benzocyclobutene (BCB).
18 . The integrated circuit chip of claim 15 , wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip.
19 . The integrated circuit chip of claim 15 , wherein said metal post comprises electroplated copper.
20 . The integrated circuit chip of claim 15 , wherein said metal post comprises an electroplated metal.
21 . The integrated circuit chip of claim 15 , wherein said metal post comprises nickel.
22 . The integrated circuit chip of claim 15 , wherein said metallization structure comprises electroplated copper.
23 . The integrated circuit chip of claim 15 , wherein said metallization structure comprises aluminum.
24 . The integrated circuit chip of claim 15 further comprising a solder bump over said top surface.
25 . The integrated circuit chip of claim 15 further comprising a metal interconnect on said polymer layer and on said top surface.
26 . The integrated circuit chip of claim 25 , wherein said metal interconnect comprises an electroplated metal.
27 . The integrated circuit chip of claim 25 , wherein said metal interconnect comprises electroplated copper.
28 . The integrated circuit chip of claim 15 further comprising a wirebonding interconnect pad connected to said metal post.