Methods and apparatuses for designing integrated circuits
View Patent ↗Methods and apparatuses for designing an integrated circuit. In one example of a method, a hardware description language (HDL) code is compiled to produce a technology independent RTL (register transfer level) netlist. A portion of an area of the IC is allocated to a specific portion of the technology independent RTL netlist. In a typical implementation of this method, the allocation restricts circuitry created from the specific portion to the portion of the IC.
1. A computer-implemented method for designing an integrated circuit (IC), said method comprising:
compiling a hardware description language (HDL) code to produce a technology independent register transfer level (RTL) netlist;
allocating a portion of a first area of said IC to a specific portion of said technology independent RTL netlist, the IC having a plurality of areas including the first area and a second area;
optimizing a design of said IC after said allocating using at least one interconnect delay between the first area and the second area of said IC to improve said optimizing; and
placing and routing components, on a data processing system, of the IC based on the optimized design of the IC the optimized design being configured to be used to create the IC.
2. A method as in claim 1 wherein optimizing comprises using a known or estimated interconnect delay.
3. A method as in claim 2 wherein optimizing optimizes a logic in said RTL netlist.
4. A method as in claim 1 further comprising mapping said RTL netlist to a target architecture to generate a technology specific netlist.
5. A method as in claim 1 further comprising including said interconnect delay in at least one timing constraint to improve said optimizing.
6. A method as in claim 5 further comprising using said at least one timing constraint to analyze said timing between an output of the first area and an input of the second area.
7. A method as in claim 6 wherein said optimizing is performed before said allocating.
8. A method as in claim 6 wherein said optimizing is performed after said allocating.
9. A machine readable storage medium having stored thereon executable program code which, when executed, causes a machine to perform a method for designing an integrated circuit (IC), said method comprising:
compiling a hardware description language (HDL) code to produce a technology independent register transfer level (RTL) netlist;
allocating a portion of a first area of said IC to a specific portion of said technology independent RTL netlist, the IC having a plurality of areas including the first area and a second area; and
optimizing a design of said IC after said allocating using at least one interconnect delay between the first area and the second area of said IC to improve said optimizing.
10. A machine readable storage medium as in claim 9 wherein optimizing comprises using a known or estimated interconnect delay.
11. A machine readable storage medium as in claim 10 wherein optimizing optimizes a logic in said RTL netlist.
12. A machine readable storage medium as in claim 9 , said method further comprising mapping said RTL netlist to a target architecture to generate a technology specific netlist.
13. A machine readable storage medium as in claim 9 , said method further comprising including said interconnect delay in at least one timing constraint to improve said optimizing.
14. A machine readable storage medium as in claim 13 , said method further comprising using said at least one timing constraint to analyze said timing between an output of the first area and an input of the second area.
15. A machine readable storage medium as in claim 14 wherein said optimizing is performed before said allocating.
16. A machine readable storage medium as in claim 14 wherein said optimizing is performed after said allocating.
17. A digital processing system for use in designing an integrated circuit (IC), said digital processing system comprising:
a display device;
a memory;
a processor coupled to said memory and said display device, said processor:
compiling a hardware description language (HDL) code to produce a technology independent register transfer level (RTL) netlist;
allocating a portion of a first area of said IC to a specific portion of said technology independent RTL netlist the IC having a plurality of areas including the first area and a second area; and
optimizing a design of said IC after said allocating using at least one interconnect delay between the first area and the second area of said IC to improve said optimizing.
18. A digital processing system as in claim 17 wherein optimizing comprises using a known or estimated interconnect delay.
19. A digital processing system as in claim 18 wherein optimizing optimizes a logic in said RTL netlist.
20. A digital processing system as in claim 17 , said processor further mapping said RTL netlist to a target architecture to generate a technology specific netlist.
21. A digital processing system as in claim 17 , said processor further including said interconnect delay in at least one timing constraint to improve said optimizing.
22. A digital processing system as in claim 21 , said processor further using said at least one timing constraint to analyze said timing between an output of the first area and an input of the second area.
23. A digital processing system as in claim 22 wherein said optimizing is performed before said allocating.
24. A digital processing system as in claim 22 wherein said optimizing is performed after said allocating.