Patent Assignment
Reel/Frame 021145/0330
Merger
Recorded: 2008-06-20
Pages: 18
Assignor
SYNPLICITY, INC., A CALIFORNIA CORPORATION
Executed: 2008-05-15
Assignee
SYNOPSYS, INC., A DELAWARE CORPORATION
700 E. MIDDLEFIELD ROAD, MOUNTAIN VIEW, CALIFORNIA, 94043
Covered Properties
(14)
Methods and Apparatuses for Designing Integrated Circuits
Methods and Apparatuses for Transient Analyses of Circuits
Methods and Apparatuses for Thermal Analysis Based Circuit Design
Placement and Routing Cells on Integrated Circuit Chips
Equivalence checking of sequential circuits
Application:
60/244,784 →
Hardware-based HDL code coverage and design analysis
Application:
60/360,627 →
Automated bottom-up and top-down partitioned synthesis flow
Application:
60/372,211 →
Enhanced hardware debugging in a hardware description language
Application:
60/387,261 →
Method and apparatus to estimate delay for logic circuit optimization
Application:
60/388,010 →
Method and apparatus for placement and routing cells on integrated circuit chips
Application:
60/388,492 →
Method and apparatus for designing integrated circuit devices with shielding
Application:
60/399,760 →
Method and apparatus for circuit partitioning and trace assignment in circuit design
Application:
60/452,314 →
Method and apparatus for automated circuit design
Application:
60/475,059 →
Method and apparatus for automated synthesis and optimization of datapaths
Application:
60/530,108 →
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.