Insulated gate transistor
A charge storage layer of first conductive type is formed on the first principal surface of a semiconductor substrate. A base layer of second conductive type is formed on the charge storage layer. Each trench formed through the base layer and the charge storage layer is lined with an insulating film and filled with a trench gate electrode. Dummy trenches are formed on both sides of each trench. Source layers of first conductive type are selectively formed in the surface of the base layer and in contact with the sidewalls of the trenches. The source layers are spaced apart from each other and arranged in the longitudinal direction of the trenches. A contact layer of second conductive type is formed in the surface of the base layer and between each two adjacent source layers arranged in the longitudinal direction of the trenches. A collector layer of second conductive type is formed on the second principal surface of the semiconductor substrate.
1. An insulated gate transistor comprising:
a semiconductor substrate of a first conductive type having a first principal surface and a second principal surface;
a charge storage layer of said first conductive type formed on said first principal surface of said semiconductor substrate;
a base layer of a second conductive type formed on said charge storage layer;
trenches formed through said base layer and said charge storage layer, said trenches being lined with a first insulating film;
trench gate electrodes each filling a respective one of said trenches;
dummy trenches formed through said base layer and said charge storage layer, respective dummy trenches being arranged adjacent to both sides of each of said trenches, said dummy trenches being lined with a second insulating film;
dummy trench gate electrodes each filling a respective one of said dummy trenches, said dummy trench gate electrodes being electrically unconnected to said trench gate electrodes;
source layers of said first conductive type selectively formed in a surface of said base layer, respective source layers being in contact with sidewalls on each side of each of said trenches, said source layers being spaced apart from each other and arranged in a longitudinal direction of said trenches;
contact layers of said second conductive type formed in said surface of said base layer and being arranged between said source layers in said longitudinal direction of said trenches, the base layer is provided between the contact layers and each of the sidewalls of the trenches and between the contact layers and each of the sidewalls of the dummy trenches, without any portion of the source layers being provided between the contact layers and each of the sidewalls of the trenches and between the contact layers and each of the sidewalls of the dummy trenches;
a collector layer of said second conductive type formed on said second principal surface of said semiconductor substrate;
an emitter electrode coupled to said source layers and said contact layers; and
a collector electrode coupled to said collector layer.
2. The insulated gate transistor as claimed in claim 1 , wherein the ratio of a width of each of said source layers to the distance between adjacent ones of each of said source layers is 0.1-0.5, said adjacent ones of each of said source layers being arranged in said longitudinal direction of said trenches, and said width of each of said source layers being measured in said longitudinal direction of said trenches.
3. The insulated gate transistor as claimed in claim 1 , wherein said dummy trench gate electrodes are held at a same potential as said emitter electrode.
4. The insulated gate transistor as claimed in claim 1 , wherein a width of each of said source layers in said longitudinal direction of said trenches is 1.0 μm or more.
5. The insulated gate transistor as claimed in claim 1 , wherein each of said source layers has a partial notch.