Top layers of metal for high performance IC's
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
1 . An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said first metallization structure, and a second opening in said passivation layer exposing a second pad of said first metallization structure, wherein said first and second pads are separate from each other, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip;
a polymer layer over said passivation layer, a third opening in said polymer layer exposing said first pad, and a fourth opening in said polymer layer exposing said second pad, wherein said polymer layer has a thickness between 2 micrometers and 30 micrometers and greater than those of said passivation layer, said first dielectric layer and said second dielectric layer; and
a second metallization structure over said polymer layer and over said first and second pads, wherein a signal goes up through said third opening, continues over a distance in a direction of a horizontal plane of said second metallization structure, and descends from said second metallization structure down to said second pad by passing through said fourth opening, wherein said second metallization structure comprises electroplated copper, and wherein said second metallization structure comprises a third metal layer having a thickness greater than those of said first and second metal layers.
2 . The integrated circuit chip of claim 1 , wherein said polymer layer comprises polyimide.
3 . The integrated circuit chip of claim 1 , wherein said second metallization structure further comprises nickel.
4 . The integrated circuit chip of claim 1 , wherein said second metallization structure further comprises tungsten.
5 . The integrated circuit chip of claim 1 , wherein said second metallization structure further comprises chromium.
6 . The integrated circuit chip of claim 1 , wherein said second metallization structure further comprises a sputtered metal.
7 . The integrated circuit chip of claim 1 , wherein said topmost nitride layer is over said topmost oxide layer.
8 . An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said first metallization structure, and a second opening in said passivation layer exposing a second pad of said first metallization structure, wherein said first and second pads are separate from each other, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip;
a polymer layer over said passivation layer, wherein said polymer layer has a thickness between 2 micrometers and 30 micrometers and greater than those of said passivation layer and said first and second dielectric layers; and
a second metallization structure over said passivation layer and over said first and second pads, wherein a signal goes up through said first opening, continues over a distance in a direction of a horizontal plane of said second metallization structure, and descends from said second metallization structure down to said second pad by passing through said second opening, wherein said second metallization structure comprises electroplated copper, and wherein said second metallization structure comprises a third metal layer having a thickness greater than those of said first and second metal layers.
9 . The integrated circuit chip of claim 8 , wherein said polymer layer comprises polyimide.
10 . The integrated circuit chip of claim 8 , wherein said second metallization structure further comprises nickel.
11 . The integrated circuit chip of claim 8 , wherein said second metallization structure further comprises tungsten.
12 . The integrated circuit chip of claim 8 , wherein said second metallization structure further comprises chromium.
13 . The integrated circuit chip of claim 8 , wherein said second metallization structure further comprises aluminum.
14 . The integrated circuit chip of claim 8 , wherein said second metallization structure further comprises a sputtered metal.
15 . The integrated circuit chip of claim 8 , wherein said second metallization structure further comprises an electroless metal.
16 . The integrated circuit chip of claim 8 , wherein said topmost nitride layer is over said topmost oxide layer.
17 . An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said first metallization structure, and a second opening in said passivation layer exposing a second pad of said first metallization structure, wherein said first and second pads are separate from each other;
a polymer layer over said passivation layer, a third opening in said polymer layer exposing said first pad, and a fourth opening in said polymer layer exposing said second pad, wherein said polymer layer has a thickness between 2 micrometers and 30 micrometers and greater than those of said passivation layer, said first dielectric layer and said second dielectric layer; and
a second metallization structure over said polymer layer and over said first and second pads, wherein a signal goes up through said third opening, continues over a distance in a direction of a horizontal plane of said second metallization structure, and descends from said second metallization structure down to said second pad by passing through said fourth opening, wherein said second metallization structure comprises electroplated copper, and wherein said second metallization structure comprises a third metal layer having a thickness greater than those of said first and second metal layers.
18 . The integrated circuit chip of claim 17 , wherein said polymer layer comprises polyimide.
19 . The integrated circuit chip of claim 17 , wherein said second metallization structure further comprises nickel.
20 . The integrated circuit chip of claim 17 , wherein said second metallization structure further comprises a sputtered metal.