Top layers of metal for high performance IC's
View Patent ↗A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
1. An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate, wherein one of said multiple devices comprises a transistor;
a first dielectric layer over said silicon substrate;
a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure comprises aluminum;
a second dielectric layer between said first and second metal layers;
a passivation layer over said metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer exposes first pad of said metallization structure, a second opening in said passivation layer exposes a second pad of said metallization structure, and a third opening in said passivation layer exposes a third pad of said metallization structure, wherein said first, second and third pads are separate from one another by an insulating material, and wherein said first, second and third pads are provided by a topmost metal layer under said passivation layer, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip;
a polymer layer over said passivation layer, wherein a fourth opening in said polymer layer exposes said first pad, a fifth opening in said polymer layer exposes said second pad, and a sixth opening in said polymer layer exposes said third pad, and wherein said polymer layer has a thickness between 2 micrometers and 30 micrometers and greater than those of said passivation layer, said first dielectric layer and said second dielectric layer; and
a clock distribution network over said polymer layer and over said first, second and third pads, wherein said clock distribution network comprises electroplated copper, wherein said first pad is connected to said second and third pads through said clock distribution network, and said second pad is connected to said third pad through said clock distribution network, and wherein said clock distribution network comprises a third metal layer having a thickness greater than those of said first and second metal layers.
2. The integrated circuit chip of claim 1 , wherein said polymer layer comprises polyimide.
3. The integrated circuit chip of claim 1 , wherein said clock distribution network further comprises nickel.
4. The integrated circuit chip of claim 1 , wherein said clock distribution network further comprises tungsten.
5. The integrated circuit chip of claim 1 , wherein said clock distribution network further comprises chromium.
6. The integrated circuit chip of claim 1 , wherein said clock distribution network further comprises a sputtered metal.
7. An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate, wherein one of said multiple devices comprises a transistor;
a first dielectric layer over said silicon substrate;
a metallization structure over said first dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure comprises aluminum;
a second dielectric layer between said first and second metal layers;
a passivation layer over said metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer exposes a first pad of said metallization structure, a second opening in said passivation layer exposes a second pad of said metallization structure, and a third opening in said passivation layer exposes a third pad of said metallization structure, wherein said first, second and third pads are separate horn one another by an insulating material, wherein said first, second and third pads are provided by a topmost metal layer under said passivation layer, and wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip;
a polymer layer over said passivation layer, wherein said polymer layer has a thickness between 2 micrometers and 30 micrometers and greater than those of said passivation layer, said first dielectric layer and said second dielectric layer; and
a clock distribution network over said passivation layer and over said first, second and third pads, wherein said clock distribution network comprises electroplated copper, wherein said first pad is connected to said second and third pads through said clock distribution network, and said second pad is connected to said third pad through said clock distribution network, and wherein said clock distribution network comprises a third metal layer having a thickness greater than those of said first and second metal layers.
8. The integrated circuit chip of claim 7 , wherein said polymer layer comprises polyimide.
9. The integrated circuit chip of claim 7 , wherein said clock distribution network further comprises nickel.
10. The integrated circuit chip of claim 7 , wherein said clock distribution network further comprises tungsten.
11. The integrated circuit chip of claim 7 , wherein said clock distribution network further comprises chromium.
12. The integrated circuit chip of claim 7 , wherein said clock distribution network further comprises a sputtered metal.
13. The integrated circuit chip of claim 7 , wherein said clock distribution network further comprises an electroless metal.
14. An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate wherein one of said multiple devices comprises a transistor;
a first dielectric layer over said silicon substrate;
a metallization structure over said fist dielectric layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said metallization structure comprises aluminum;
a second dielectric layer between said first and second metal layers;
a passivation layer over said metallization structure and over said first and second dielectric layers, wherein a first opening in said passivation layer exposes a first pad of said metallization structure, a second opening in said passivation layer exposes a second pad of said metallization structure, and a third opening in said passivation layer exposes a third pad of said metallization structure, wherein said first, second and third pads are separate from one another by an insulating material, wherein said first, second and third pads are provided by a topmost metal layer under said passivation layer, and wherein said passivation layer comprises an oxide layer and a nitride layer over said oxide layer; and
a clock distribution network over said passivation layer and over said first, second and third pads, wherein said clock distribution network comprises electroplated copper, wherein said first pad is connected to said second and third pads through said clock distribution network, and said second pad is connected to said third pad through said clock distribution network, and wherein said clock distribution network comprises a third metal layer having a thickness greater than those of said first and second metal layers.
15. The integrated circuit chip of claim 14 further comprising a polymer layer over said passivation layer, wherein a fourth opening in said polymer layer exposes said first pad, a fifth opening in said polymer layer exposes said second pad, and a sixth opening in said polymer layer exposes said third pad, wherein said clock distribution network is over said polymer layer.
16. The integrated circuit chip of claim 15 , wherein said polymer layer comprises polyimide.
17. The integrated circuit chip of claim 15 , wherein said polymer layer comprises benzocyclobutene.
18. The integrated circuit chip of claim 15 , wherein said polymer layer has a thickness between 2 and 30 micrometers.
19. The integrated circuit chip of claim 14 , wherein said clock distribution network further comprises nickel.
20. The integrated circuit chip of claim 14 , wherein said clock distribution network further comprises a sputtered metal.