Top layers of metal for high performance IC's
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
1 . An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said first metallization structure, a second opening in said passivation layer exposing a second pad of said first metallization structure, and a third opening in said passivation layer exposing a third pad of said first metallization structure, wherein said first, second and third pads are separate from one another, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip;
a second metallization structure over said passivation layer and over said first, second and third pads, wherein said second metallization structure comprises electroplated copper, wherein said second metallization structure comprises a third metal layer and a fourth metal layer over said third metal layer, said third metal layer having a thickness greater than those of said first and second metal layers, and said fourth metal layer having a thickness greater than those of said first and second metal layers, and wherein said first pad is connected to said second and third pads through a ground distribution structure of said second metallization structure, and said second pad is connected to said third pad through said ground distribution structure; and
a first polymer layer between said third and fourth metal layers, wherein said first polymer layer has a thickness greater than those of said passivation layer, said first dielectric layer and said second dielectric layer.
2 . The integrated circuit chip of claim 1 further comprising a second polymer layer over said passivation layer, a fourth opening in said second polymer layer exposing said first pad, a fifth opening in said second polymer layer exposing said second pad, and a sixth opening in said second polymer layer exposing said third pad, wherein said second metallization structure and said first polymer layer are over said second polymer layer
3 . The integrated circuit chip of claim 2 , wherein said second polymer layer comprises polyimide.
4 . The integrated circuit chip of claim 2 , wherein said second polymer layer has a thickness between 2 and 30 micrometers.
5 . The integrated circuit chip of claim 1 , wherein said first polymer layer comprises polyimide.
6 . The integrated circuit chip of claim 1 , wherein said second metallization structure further comprises nickel.
7 . The integrated circuit chip of claim 1 , wherein said second metallization structure further comprises a sputtered metal.
8 . An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises electroplated copper;
a second dielectric layer between said first and second metal layers;
an inorganic layer over said first and second dielectric layers;
a first polymer layer over said inorganic layer, a first opening in said first polymer layer exposing a first pad of said first metallization structure, a second opening in said first polymer layer exposing a second pad of said first metallization structure, and a third opening in said first polymer layer exposing a third pad of said first metallization structure, wherein said first, second and third pads are separate from one another, wherein said first polymer layer has a thickness between 2 micrometers and 30 micrometers and greater than those of said inorganic layer, said first dielectric layer and said second dielectric layer; and
a second metallization structure over said first polymer layer and over said first, second and third pads, wherein said second metallization structure comprises electroplated copper, wherein said second metallization structure comprises a third metal layer and a fourth metal layer over said third metal layer, said third metal layer having a thickness greater than those of said first and second metal layers, and said fourth metal layer having a thickness greater than those of said first and second metal layers, and wherein said first pad is connected to said second and third pads through a ground distribution structure of said second metallization structure, and said second pad is connected to said third pad through said ground distribution structure; and
a second polymer layer between said third and fourth metal layers, wherein said second polymer layer has a thickness greater than those of said inorganic layer, said first dielectric layer and said second dielectric layer.
9 . The integrated circuit chip of claim 8 , wherein said first polymer layer comprises polyimide.
10 . The integrated circuit chip of claim 8 , wherein said first polymer layer has a thickness between 2 micrometers and 30 micrometers.
11 . The integrated circuit chip of claim 8 , wherein said second polymer layer comprises polyimide.
12 . The integrated circuit chip of claim 8 , wherein said second metallization structure further comprises nickel.
13 . The integrated circuit chip of claim 8 , wherein said second metallization structure further comprises a sputtered metal.
14 . The integrated circuit chip of claim 8 , wherein said inorganic layer comprises nitride.
15 . An integrated circuit chip comprising:
a silicon substrate;
multiple devices in and on said silicon substrate;
a first dielectric layer over said silicon substrate;
a first metallization structure over said first dielectric layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, and wherein said first metallization structure comprises aluminum;
a second dielectric layer between said first and second metal layers;
a passivation layer over said first metallization structure and over said first and second dielectric layers, a first opening in said passivation layer exposing a first pad of said first metallization structure, a second opening in said passivation layer exposing a second pad of said first metallization structure, and a third opening in said passivation layer exposing a third pad of said first metallization structure, wherein said first, second and third pads are separate from one another, wherein said passivation layer comprises a topmost nitride layer of said integrated circuit chip and a topmost oxide layer of said integrated circuit chip, wherein said topmost nitride layer is over said topmost oxide layer;
a second metallization structure over said passivation layer and over said first, second and third pads, wherein said second metallization structure comprises electroplated copper, wherein said second metallization structure comprises a third metal layer and a fourth metal layer over said third metal layer, said third metal layer having a thickness greater than those of said first and second metal layers, and said fourth metal layer having a thickness greater than those of said first and second metal layers, and wherein said first pad is connected to said second and third pads through a ground distribution structure of said second metallization structure, and said second pad is connected to said third pad through said ground distribution structure; and
a first polymer layer between said third and fourth metal layers, wherein said first polymer layer has a thickness greater than those of said passivation layer, said first dielectric layer and said second dielectric layer.
16 . The integrated circuit chip of claim 15 further comprising a second polymer layer over said passivation layer, a fourth opening in said second polymer layer exposing said first pad, a fifth opening in said second polymer layer exposing said second pad, and a sixth opening in said second polymer layer exposing said third pad, wherein said second metallization structure and said first polymer layer are over said second polymer layer.
17 . The integrated circuit chip of claim 16 , wherein said second polymer layer comprises polyimide.
18 . The integrated circuit chip of claim 16 , wherein said second polymer layer has a thickness between 2 micrometers and 30 micrometers.
19 . The integrated circuit chip of claim 15 , wherein said first polymer layer comprises polyimide.
20 . The integrated circuit chip of claim 15 , wherein said second metallization structure further comprises nickel.
21 . The integrated circuit chip of claim 15 , wherein said second metallization structure further comprises a sputtered metal.