Stacked die packages
View Patent ↗A stacked die semiconductor package that includes a substrate with a plurality of adhesive portions arranged in a manner to create at least one gap between the adhesive portions. The package also includes a first semiconductor chip having a non-active surface in contact with the adhesive portions, and an active surface being electrically connected to the substrate. In the package, a second semiconductor chip the non-active surface of the second semiconductor chip is attached to the non-active surface of the first semiconductor chip by a layer of adhesive therebetween. The active surface of the second semiconductor chip is electrically connected to the substrate. An encapsulant material covers the first and second semiconductor chips and their associated electrical connections. The encapsulating material fills the at least one gap between the plurality of adhesive portions and thereby encapsulates the second semiconductor chip and its associated electrical connection.
1. A semiconductor package comprising:
a substrate having a top surface, a bottom surface and a cavity through the top and bottom surfaces of the substrate, the top surface comprising a plurality of adhesive portions arranged in a manner to create at least one gap between the adhesive portions, wherein a bottom of the at least one gap is defined by the top surface of the substrate;
a first semiconductor chip having an active surface and a non-active surface, the non-active surface of the first semiconductor chip being in contact with the adhesive portions, and the active surface of the first semiconductor chip being electrically connected to the substrate;
a second semiconductor chip having an active surface and a non-active surface, the non-active surface of the second semiconductor chip being attached to the non-active surface of the first semiconductor chip by a layer of adhesive therebetween, and the active surface of the second semiconductor chip being electrically connected to the substrate, wherein the cavity accommodates the second semiconductor chip; and
an encapsulant material covering the first and second semiconductor chips, their associated electrical connections, and filling the at least one gap between the adhesive portions between the first semiconductor chip and substrate in one step.
2. The semiconductor package of claim 1 , wherein said electrical connection is made by a bond wire.
3. The semiconductor package of claim 1 , wherein the second semiconductor chip has a smaller surface area than that of the first semiconductor chip.
4. The semiconductor package of claim 1 , wherein the active surface of the second semiconductor chip is electrically connected to the bottom surface of the substrate through the cavity.
5. The semiconductor package of claim 1 , further comprising a third semiconductor chip attached to the active surface of the first semiconductor chip by a layer of adhesive.
6. A semiconductor package comprising:
a substrate having a top surface, a bottom surface and a cavity extending at least partially from the top surface toward the bottom surface, the top surface comprising a plurality of adhesive portions arranged in a manner to create at least one gap between the adhesive portions, wherein a bottom of the at lest one gap is defined by the top surface of the substrate;
a first semiconductor chip having an active surface and a non-active surface, the non-active surface of the first semiconductor chip being in contact with the adhesive portions, and the active surface of the first semiconductor chip being electrically connected to the substrate;
a second semiconductor chip having an active surface and a non-active surface, the non-active surface of the second semiconductor chip being attached to a portion of the substrate in the cavity by a layer of adhesive therebetween, and the active surface of the second semiconductor chip being electrically connected to the substrate; and
an encapsulant material covering the first and second semiconductor chips and their associated electrical connections, wherein the at least one gap between the adhesive portions on the substrate allows the encapsulant material to flow therethrough and encapsulate the first and second semiconductor chips and their associated electrical connections in one step.
7. The semiconductor package of claim 6 , wherein the active surface of the second semiconductor chip is electrically connected to the top surface of the substrate.
8. The semiconductor package of claim 6 , wherein the active surface of the second semiconductor chip is electrically connected to the floor of the cavity.
9. The semiconductor package of claim 6 , further comprising a third semiconductor chip attached to the active surface of the first semiconductor chip by a layer of adhesive.
10. The semiconductor package of claim 6 , wherein said first semiconductor chip does not fully cover the cavity.
11. A method of manufacturing a semiconductor package comprising:
(a) providing a substrate having a cavity extending from a top surface to a bottom surface, a plurality of adhesive portions on a top surface of the substrate, the plurality of adhesive portions arranged in a manner to create at least one gap between the adhesive portions, wherein a bottom of the at least one gap is defined by the top surface of the substrate;
(b) attaching a non-active surface of a first semiconductor chip to the adhesive portions on the top surface of the substrate;
(c) attaching a non-active surface of a second semiconductor chip to the non-active surface of the first semiconductor chip using a layer of adhesive therebetween, the active surface of the second semiconductor chip resides partially within the cavity;
(d) electrically connecting active surfaces of the first and semiconductor chips to the substrate; and
(e) covering the first and second semiconductor chips and their associated electrical connections with an encapsulant material, wherein during encapsulation, the at least one gap between the adhesive portions on the substrate allows the encapsulant material to flow therethrough and encapsulate the first and second semiconductor chips and their associated electrical connections on one step.
12. The method of claim 11 , wherein step (d) comprises electrically connecting the first and second semiconductor chips to the substrate using bond wires.
13. The method of claim 11 , wherein in step (c) the second semiconductor chip has a smaller surface area than the first semiconductor chip.
14. The method of claim 11 , wherein step (d) comprises electrically connecting an active surface of the second semiconductor chip to the bottom surface of the substrate through the cavity.
15. The method of claim 11 , further comprising:
(f) attaching a third semiconductor chip to the active surface of the first semiconductor ship by a layer of adhesive.
16. A method of manufacturing a semiconductor package comprising:
(a) providing a substrate having a cavity extending at least partially from a top surface to a bottom surface, and a plurality of adhesive portions on a top surface of the substrate, the plurality of adhesive portions arranged in a manner to create at least one gap between the adhesive portions, wherein a bottom of the at least one gap is defined by the top surface of the substrate;
(b) attaching a non-active surface of a first semiconductor chip to the adhesive portions on the top surface of the substrate;
(c) attaching a non-active surface of a second semiconductor chip to a portion of the substrate in the cavity using a layer of adhesive therebetween;
(d) electrically connecting active surfaces of the first and semiconductor chips to the substrate; and
(e) covering the first and second semiconductor chips and their associated electrical connections with an encapsulant material, wherein during encapsulation, the at least one gap between the adhesive portions on the substrate allows the encapsulant material to flow therethrough and encapsulate the first and second semiconductor chips and their associated electrical connections in one step.
17. The method of claim 16 , wherein step (d) comprises electrically connecting an active surface of the second semiconductor chip to the floor of the cavity.
18. The method of claim 16 , further comprising:
(f) attaching a third semiconductor chip to the active surface of the first semiconductor ship by a layer of adhesive.