Method of forming semiconductor device
View Patent ↗Embodiments relate to a method of forming a 90 nm semiconductor device, including forming an isolation film within a semiconductor substrate in which a pMOS region and an nMOS region are defined. A first mask is formed to shield the nMOS region by using a DUV photoresist having a thickness of approximately 0.7 to 0.75 μm. Ions are implanted into the pMOS region to form a p type well. A second mask is formed to shield the pMOS region by using a DUV photoresist having a thickness of approximately 0.7 to 0.75 μm. Ions are implanted into the nMOS region to form an n type well. A gate oxide film and a gate is formed over the semiconductor substrate. A low-concentration impurity may be implanted by using the gate as a mask. An LDD region may be formed. A sidewall spacer may be formed over both sidewalls of the gate. A high-concentration impurity is implanted by using the sidewall spacer as a mask, forming a source/drain region.
1. A method comprising:
forming an isolation film within a semiconductor substrate in which a pMOS region and an nMOS region are defined;
forming a first mask to shield an NMOS region by using a deep ultraviolet photoresist having a thickness of approximately 0.7 to 0.75 μm, and implanting ions into the pMOS region to form a p type well;
forming a second mask to shield the pMOS region by using a deep ultraviolet photoresist having a thickness of approximately 0.7 to 0.75 μm, and implanting ions into the nMOS region to form an n type well.
2. The method of claim 1 , wherein the thickness of the deep ultraviolet photoresist is set based on an implant state condition and secondary ion mass spectrometry analysis.
3. The method of claim 2 , wherein the implant state condition includes at least one of a dopant, energy, dose and tilt/twist variation information.
4. The method of claim 3 , wherein the first mask is suitable as a barrier with respect to a dopant 11B+ at an energy of approximately 30 KeV or less.
5. The method of claim 3 , wherein the first mask is used for a pMOS lightly doped drain.
6. The method of claim 3 , wherein a top loss of the photoresist is approximately 250 nm or less.
7. The method of claim 3 , wherein the first mask is suitable as a barrier with respect to a dopant 31P+ at an energy of approximately 30 KeV or less.
8. The method of claim 3 , wherein the first mask is used as an nMOS lightly doped drain.
9. The method of claim 1 , wherein the device method follows 90 nm design rules to form a 90 nm semiconductor device.
10. The method of claim 1 , comprising forming a gate oxide film and a gate over the semiconductor substrate.
11. The method of claim 10 , comprising implanting a low-concentration impurity by using the gate as a mask, forming a lightly doped drain region.
12. The method of claim 11 , comprising forming a sidewall spacer over both sidewalls of the gate.
13. The method of claim 12 , comprising implanting a high-concentration impurity by using the sidewall spacer as a mask, forming a source/drain region.
14. The method of claim 1 , comprising forming a p type field stop layer in the nMOS region.
15. The method of claim 1 , comprising forming an n type field stop layer in the pMOS region.
16. An apparatus comprising:
an isolation film formed within a semiconductor substrate in which a pMOS region and an nMOS region are defined;
a p type well formed by implanting ions into the pMOS region after forming a first mask to shield the nMOS region by using a deep ultraviolet photoresist having a thickness of approximately 0.7 to 0.75 μm;
an n type well formed by implanting ions into the NMOS region after forming a second mask to shield the pMOS region by using a deep ultraviolet photoresist having a thickness of approximately 0.7 to 0.75 μm.
17. The apparatus of claim 16 , comprising a gate oxide film and a gate formed over the semiconductor substrate.
18. The apparatus of claim 17 , comprising a lightly doped drain region formed by implanting a low-concentration impurity by using the gate as a mask.
19. The apparatus of claim 18 , comprising a sidewall spacer formed over both sidewalls of the gate.
20. The apparatus of claim 19 , comprising a source/drain region formed by implanting a high-concentration impurity by using the sidewall spacer as a mask.