IP Library Granted Patent US 7,611,041
Granted Patent B2
US 7,611,041 · App. 11/847,687 · Granted Nov 3, 2009

Semiconductor device, manufacturing method and apparatus for the same

Assignee: NEC Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,611,041
App. No.
11/847,687
Granted
Nov 3, 2009
Kind
B2
Abstract

A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.

Claims (20)

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming, on a wiring layer, an under-bump layer including first metal which is to form a first intermetallic compound at an interface through reaction with alloy solder;

supplying alloy solder having second metal different from main component metal added thereto; and

forming an alloy layer at an interface between the under-bump layer and the alloy solder by temporary fusing the alloy solder before cooling, wherein the alloy layer is a combination of the first intermetallic compound and a second intermetallic compound of the main component metal of the alloy solder and the second metal.

2. The semiconductor device manufacturing method according to claim 1 , further comprising the step of, before forming the under-bump layer on the wiring layer, forming a contact layer for maintaining adhesion of the wiring layer and the under-bump layer.

3. The semiconductor device manufacturing method according to claim 1 , wherein, when forming the solder bump, fusing of the alloy solder and deposition of the intermetallic compound are carried out by setting a temperature of an interface of the solder bump with the under-bump layer to lower than a temperature at the top of the solder bump on a specified temperature gradient.

4. The semiconductor device manufacturing method according to claim 1 , wherein, when forming the solder bump, fusing of the alloy solder and deposition of the intermetallic compound are carried out by mounting the semiconductor device on a stage and causing a heating plate and a cooling plate movably provided at a lower part of the stage to be sequentially brought into contact with the stage.

5. The semiconductor device manufacturing method according to claim 4 , wherein, at the time of heating using the heating plate, the semiconductor device is also heated from above by a non-contact heater provided at an upper part of the semiconductor device, and at the time of cooling using the cooling plate, while continuing heating using the non-contact heater, a temperature gradient between the top of solder bump and the interface of the solder bump with the under-bump layer is increased to promote deposition to the interface of the intermetallic compound with the under-bump layer.

6. The semiconductor device manufacturing method according to claim 4 , wherein cooling using the cooling plate is carried out at cooling rate of at least 2° C. per second.

7. The semiconductor device manufacturing method according to claim 4 , wherein the heating using the heating plate and the cooling using the cooling plate are carried out under a vacuum atmosphere of a specified gas.

8. The semiconductor device manufacturing method according to claim 7 , wherein the specified gas includes one of an inert gas and a reductive gas.

9. The semiconductor device manufacturing method according to claim 8 , wherein the inert gas comprises one of nitrogen and argon, and the reductive gas comprises one of hydrogen and a mixed gas including hydrogen.

10. The semiconductor device manufacturing method according to claim 1 , wherein the under-bump layer is formed from one of a single film and a laminate of a plurality of films made of one selected from a group consisting of nickel, nickel alloy, copper and copper alloy which are formed by sputtering.

11. The semiconductor device manufacturing method according to claim 1 , wherein the under-bump layer is formed from one of a single film and a laminate of a plurality of films made of one selected from a group consisting of nickel, nickel alloy, copper and copper alloy which are formed by one of nonelectrolytic plating and electrolytic plating.

12. The semiconductor device manufacturing method according to claim 1 , wherein the under-bump layer is formed as a laminate film of a film made of one selected from a group consisting of nickel, nickel alloy, copper and copper alloy which are formed by the spattering and a film made of one selected from a group consisting of nickel, nickel alloy, copper and copper alloy which are formed by one of nonelectrolytic plating and electrolytic plating.

13. The semiconductor device manufacturing method according to claim 1 , wherein the alloy solder is supplied as one of a ball and pellet formed to a specified amount.

14. The semiconductor device manufacturing method according to claim 1 , wherein the alloy solder is supplied as solder paste.

15. The semiconductor device manufacturing method according to claim 1 , wherein the main component of the alloy solder is tin.

16. The semiconductor device manufacturing method according to claim 15 , wherein a second main component of the alloy solder after tin is silver.

17. The semiconductor device manufacturing method according to claim 15 , wherein copper is added to the alloy solder.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2015
From: NEC CORPORATION
To: GODO KAISHA IP BRIDGE 1
Reel/Frame 034834/0806 →
Priority Claims (2)
JP 2001-005977 · Jan 15, 2001 · national
JP 2001-170787 · Jun 6, 2001 · national
Continuity (3)
Division 1114475300 · Jun 6, 2005
Division 1004322500 · Jan 14, 2002
Related Publication 20070295786A1 · Dec 27, 2007