Nano-Enabled Memory Devices and Anisotropic Charge Carrying Arrays
Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device. In a multistate memory device which comprises one or more quantum dots or molecules having a plurality of discrete energy levels, a method is disclosed for charging and/or discharging the device which comprises filling each of the plurality of discrete energy levels of each dot or molecule with one or more electrons, and subsequently removing individual electrons at a time from each discrete energy level of the one or more dots or molecules.
1 . A method for fabricating a memory device, comprising:
(a) forming a source region and a drain region in a substrate thereby defining a channel region therebetween;
(b) forming a tunnel dielectric layer on the substrate over at least the channel region of the substrate;
(c) depositing or forming a barrier layer comprising a nitrogen containing compound overlying the tunnel dielectric layer; and
(c) depositing a solution comprising a population of metal quantum dots as a film on the barrier layer.
2 . The method of claim 1 , wherein the barrier layer comprises silicon nitride.
3 . The method of claim 1 , wherein the barrier layer comprises silicon oxynitride.
4 . The method of claim 1 , wherein the barrier layer comprises alumina.
5 . The method of claim 1 , further comprising forming a gate contact above the metal quantum dots.
6 . The method of claim 1 , wherein the metal quantum dots comprise palladium.
7 . The method of claim 1 , wherein said metal quantum dots are made from ruthenium.
8 . The method of claim 1 , further comprising:
(d) forming each metal quantum dot to have a metal core and a shell, wherein the shell surrounds the core for each quantum dot.
9 . The method of claim 1 , wherein step (d) comprises:
oxidizing each quantum dot to form the shell as an oxidized layer around the metal core of each dot
10 . A method comprising forming a charge storage layer of a memory device comprising a population of metal quantum dots deposited from solution in a film onto a substrate and forming a barrier layer comprising a nitrogen containing compound between the substrate and the metal quantum dots.
11 . The method of claim 10 , wherein the barrier layer comprises silicon nitride.
12 . The method of claim 10 , wherein the barrier layer comprises silicon oxynitride.
13 . The method of claim 10 , wherein the barrier layer comprises alumina.
14 . The method of claim 10 , further comprising forming a gate contact overlying the metal quantum dots.
15 . The method of claim 10 , wherein the metal quantum dots comprise palladium.
16 . The method of claim 10 , wherein said metal quantum dots are made from ruthenium.
17 . The method of claim 1 , wherein said tunnel dielectric layer comprises silicon dioxide and said depositing or forming a barrier layer comprises nitriding said silicon dioxide layer.
18 . The method of claim 1 , wherein said tunnel dielectric layer comprises silicon dioxide and said depositing or forming a barrier layer comprises depositing the nitrogen-containing compound on said silicon dioxide layer.
19 . The method of claim 1 , wherein said depositing a solution comprising a population of metal quantum dots as a film on the barrier layer comprises spin-casting the solution on the barrier layer.