Integrated circuit with dielectric layer

1. A method of fabricating an integrated circuit device, the method comprising:

forming a dielectric layer on a semiconductor substrate, the dielectric layer being in an amorphous state and having a crystallization temperature, at and above which the dielectric layer undergoes a transition from the amorphous state to a crystalline state;

doping the dielectric layer with a dopant;

forming a covering layer on the dielectric layer at a first temperature, the first temperature being below the crystallization temperature, the covering layer comprising a conductive material; and

heating the dielectric layer to a second temperature, the second temperature being equal to or greater than the crystallization temperature.

2. The method of claim 1 , wherein after heating the dielectric layer, the dielectric layer comprises a domain of the dielectric layer in a crystalline state, wherein a first lattice constant of the crystalline state is perpendicular to an interface between the dielectric layer and the substrate and a second lattice constant of the crystalline state is parallel to the interface, and wherein a ratio of the second lattice constant divided by the first lattice constant is equal to or greater than 1, and less than 1.1.

3. The method of claim 2 , wherein the ratio of the second lattice constant divided by the first lattice constant is equal to or greater than 1, and less than 1.04.

4. The method of claim 1 , comprising stressing the dielectric layer after the heating by at least one of compressing, straining, stretching, and expanding the dielectric layer, and wherein the dielectric layer after the heating comprises a ferroelectric domain.

5. The method of claim 2 , wherein the dielectric layer comprises hafnium-silicon-oxide and the ratio of the second lattice constant divided by the first lattice constant is equal to or greater than 1, and less than 1.04, and wherein the dielectric layer comprises silicon in a concentration in the range of 0.5% to 20% and wherein the doping of the dielectric layer is conducted during the forming of the dielectric layer.

6. The method of claim 1 , wherein the dielectric layer comprises any from the group comprising a transition metal oxide, zirconium, zirconium oxide, hafnium, hafnium oxide, lead zirconium titanate, tantalum oxide, barium strontium titanate, and silicon nitride, and wherein the dopant comprises any from the group comprising silicon, aluminium, lanthanum, yttrium, erbium, calcium, magnesium, strontium, and a rare earth element.

7. The method of claim 6 , wherein a concentration of the dopant of the dielectric layer is in the range of 0.5% to 20%.

8. The method of claim 1 , further comprising:

forming a stress inducing layer on the covering layer; and

removing the stress inducing layer after the heating of the dielectric layer to the second temperature.

9. The method of claim 1 , wherein the integrated circuit device is any of the group comprising a capacitor and a transistor.

10. A method of fabricating an integrated circuit device, the method comprising:

forming a dielectric layer on a semiconductor substrate, the dielectric layer being in an amorphous state and having a crystallization temperature, at and above which the dielectric layer undergoes a transition from the amorphous state to a crystalline state;

doping the dielectric layer with a dopant; and

forming a conductive layer on the dielectric layer at a first temperature, the first temperature being equal to or greater than the crystallization temperature such that while forming the conductive layer a crystalline state is induced in the dielectric layer.

11. The method of claim 10 , wherein a first lattice constant of the crystalline state is perpendicular to an interface between the dielectric layer and the substrate and a second lattice constant of the crystalline state is parallel to the interface, and wherein a ratio of the second lattice constant divided by the first lattice constant is equal to or greater than 1, and less than 1.1.

12. The method of claim 11 , wherein the ratio of the second lattice constant divided by the first lattice constant is equal to or greater than 1, and less than 1.04.

13. The method of claim 10 , wherein forming the dielectric layer on the semiconductor substrate comprises forming the dielectric layer on an electrode formed in the semiconductor substrate.

14. The method of claim 10 , wherein forming the dielectric layer comprises forming a dielectric layer comprising one of a transition metal oxide, zirconium, zirconium oxide, hafnium, hafnium oxide, lead zirconium titanate, tantalum oxide, barium strontium titanate, and silicon nitride.

15. The method of claim 10 , wherein doping the dielectric layer comprises doping the dielectric layer with a dopant comprising one of silicon, aluminium, lanthanum, yttrium, erbium, calcium, magnesium, strontium, and a rare earth element.

16. The method of claim 10 , wherein forming the conductive layer comprises forming a conductive layer comprising one of titanium nitride, tantalum nitride, tungsten nitride, niobium nitride, carbon, iridium, and ruthenium.

17. The method of claim 10 , wherein a concentration of the dopant of the dielectric layer is in the range of 0.5% to 20%.

18. The method of claim 11 , wherein the dielectric layer comprises hafnium-silicon-oxide and the ratio of the second lattice constant divided by the first lattice constant is equal to or greater than 1, and less than 1.04, and wherein the dielectric layer comprises silicon in a concentration in the range of 0.5% to 20% and wherein the doping of the dielectric layer is conducted during the forming of the dielectric layer.

19. A method of fabricating a transistor, the method comprising:

depositing a dielectric layer over a semiconductor substrate including a first source/drain region and a second source/drain region, the dielectric layer being in an amorphous state and having a crystallization temperature, at and above which the dielectric layer undergoes a transition from the amorphous state to a crystalline state;

doping the dielectric layer with a dopant;

depositing a gate electrode layer over the dielectric layer at a first temperature, the first temperature being below the crystallization temperature; and

heating the dielectric layer to a second temperature, the second temperature being equal to or greater than the crystallization temperature.

20. A method of fabricating a transistor, the method comprising:

forming an insulating layer over a semiconductor substrate including a first source/drain region and a second source/drain region;

depositing a dielectric layer over the insulating layer, the dielectric layer being in an amorphous state and having a crystallization temperature, at and above which the dielectric layer undergoes a transition from the amorphous state to a crystalline state;

doping the dielectric layer with a dopant;

depositing a gate electrode layer over the dielectric layer at a first temperature, the first temperature being below the crystallization temperature; and

heating the dielectric layer to a second temperature, the second temperature being equal to or greater than the crystallization temperature,

wherein the dielectric layer after the heating comprises a ferroelectric domain.

21. A method of fabricating a capacitor, the method comprising:

depositing a dielectric layer over a first electrode layer, the dielectric layer being in an amorphous state and having a crystallization temperature, at and above which the dielectric layer undergoes a transition from the amorphous state to a crystalline state;

doping the dielectric layer with a dopant;

depositing a second electrode layer over the dielectric layer at a first temperature, the first temperature being below the crystallization temperature; and

heating the dielectric layer to a second temperature, the second temperature being equal to or greater than the crystallization temperature.

22. The method of claim 21 , wherein the capacitor comprises a planar capacitor.

23. The method of claim 21 , wherein the capacitor comprises a trench capacitor.