Flash memory device with single-poly structure and method for manufacturing the same
View Patent ↗A flash memory device has a single-poly structure. A method for manufacturing the flash device includes forming an oxide layer over a semiconductor substrate having a P-well region or N-well region. A shallow trench isolation (STI) may be formed in the semiconductor substrate and the oxide layer. A drift region may be formed by injecting a dopant into a part of the P-well region or N-well region. A gate oxide layer and a poly-silicon layer may be formed over the well region, the drift region, and the STI. A control gate pattern may be formed by patterning the gate oxide layer and the poly-silicon layer. A source region and a drain region may be formed on opposite sides of the control gate pattern. A silicon nitride layer may be deposited over the control gate pattern and etching the silicon nitride layer to form a spacer around a sidewall of the control gate pattern. A plurality of insulating layers may be formed over the control gate pattern, and via-patterns may be electrically connected to the source region and the drain region, respectively. A drain electrode and a source electrode may be electrically connected to the via-patterns, respectively.
1. A method comprising:
forming an oxide layer over a semiconductor substrate having a well region;
forming a shallow trench isolation in the semiconductor substrata and the oxide layer;
forming a drift region by injecting a dopant into a part of the well region;
sequentially forming a gate oxide layer and a poly-silicon layer over the well region, the drift region, and the shallow trench isolation;
forming a control gate pattern by patterning the gate oxide layer and the poly-silicon layer;
forming a source region and a drain region at opposite sides of the control gate pattern;
depositing a silicon nitride layer on the control gate pattern and etching the silicon nitride layer to form a spacer around a sidewall of the control gate pattern.
2. The method of claim 1 , wherein, in the formation of the control gate pattern, the poly-silicon layer is a single layer.
3. The method of claim 1 , wherein, in the formation of the drift region, the drift region includes a side portion overlapped with the control gate pattern, and has a depth deeper than that of the source region.
4. The method according to claim 1 , wherein, in the formation of the control gate pattern, the control gate pattern includes a floating poly gate of a high-voltage P-type metal oxide semiconductor.
5. The method of claim 1 , wherein, in the formation of the source region and the drain region, the source region is doped with a n+ dopant and a p+ dopant.
6. The method of claim 1 , wherein, in the formation of the drift region, the semiconductor substrate is a P-type substrate, the well is of the N-well region, and a P-type dopant is injected into an upper portion of the N-well region to form a P-drift region.
7. The method of claim 1 , wherein, in the formation of the drift region, the semiconductor substrate is an N-type substrate, the well is a P-well region, and an N-type dopant is injected into an upper portion of the P-well region to form an N-drift region.
8. The method of claim 1 , wherein a flash memory device is formed by the method.
9. The method of claim 1 , comprising forming a plurality of insulating layers on the control gate pattern, and forming via-patterns to be electrically connected to the source region and the drain region, respectively.
10. The method of claim 9 , comprising providing a drain electrode and a source electrode to be electrically connected to the via-patterns, respectively.
11. An apparatus comprising:
a control gate pattern provided on a semiconductor substrate having a well region;
a shallow trench isolation layer in the semiconductor substrate;
a source region and a drain region provided at sides of the control gate pattern, wherein the drain region is adjacent to the shallow trench isolation layer;
a drift region formed in a part of the well region in a side direction of the drain region, wherein the drift region is between the control gate pattern and the shallow trench isolation layer;
via-patterns to be electrically connected to the source region and the drain region, respectively; and
a drain electrode and a source electrode to be electrically connected to upper ends of the via-patterns, respectively.
12. The apparatus of claim 11 , wherein the control gate pattern includes a single poly-silicon layer.
13. The apparatus of claim 11 , wherein the drift region includes a side portion overlapped with the control gate pattern, and the drift region is deeper than the source region.
14. The apparatus of claim 11 , wherein the control gate pattern includes a floating poly gate of a high-voltage PMOS.
15. The apparatus of claim 11 , wherein the source region is doped with an n+ dopant and a p+ dopant.
16. The apparatus of claim 11 , wherein the semiconductor substrate is a P-type substrate, the well region is an N-well region, and the drift region is a P-drift region formed by injecting a P-type dopant into an upper portion of the N-well region.
17. The apparatus of claim 11 , wherein the semiconductor substrate is a N-type substrate, the well region is a P-well region, and the drift region is an N-drift region formed by injecting an N-type dopant into an upper portion of the P-well region.
18. The apparatus of claim 11 , comprising a spacer around a sidewall of the control gate pattern.
19. The apparatus of claim 11 , wherein the apparatus is a flash memory device with a single-poly structure.