Level-conversion circuit

1. A level-conversion circuit, comprising:

a PMOS-driver control unit;

an NMOS-driver control unit;

a PMOS-side power-source control unit;

an NMOS-side power-source control unit;

an output unit; and

an output-feedback unit that outputs an inverted output signal, wherein,

each of the PMOS-driver control unit and the NMOS-driver control unit inverts a small-amplitude input signal and transmits the inverted small-amplitude input signal to the output unit, and

each of the PMOS-side power-source control unit and the NMOS-side power-source control unit establishes electrical continuity between the output unit and at least one power source upon receiving the inverted output signal so that the output unit transmits a large-amplitude output signal.

2. The level-conversion circuit according to claim 1 , wherein,

each of the PMOS-side power-source control unit and the NMOS-side power-source control unit transmits a large current to the output unit over a period of time, during which the output signal is delayed.

3. The level-conversion circuit of claim 1 ,

the output unit including a first transistor for transmitting a first power-source-level large-amplitude output signal and a second transistor for transmitting a second power-source-level large-amplitude output signal;

the PMOS-side power-source control unit including third and fourth transistors; and

the NMOS-side power-source control unit including fifth and sixth transistors,

wherein, when the first transistor is turned on, the third transistor is turned on, the third transistor is turned off after the second power-source-level large-amplitude output signal transitions to the first power-source-level large-amplitude output signal, and the fourth transistor is turned on, and p 1 when the second transistor is turned on, the fifth transistor is turned off after the first power-source-level large-amplitude output signal transitions to the second power-source-level large-amplitude output signal, and the sixth transistor is turned on.

4. The level-conversion circuit according to claim 3 , wherein,

each of the third and sixth transistors is turned on after the first power-source-level large-amplitude output signal transitions to the second power-source-level large-amplitude output signal, and

each of the fourth and fifth transistors is turned on after the second power-source-level large-amplitude output signal transitions to the first power-source-level large-amplitude output signal.

5. The level-conversion circuit according to claim 3 , wherein

the PMOS-driver control unit receives a third power-source-level small-amplitude input signal and a fourth power-source-level small-amplitude input signal; and

the NMOS-driver control unit receives the third power-source-level small-amplitude input signal and the fourth power-source-level small-amplitude input signal,

wherein, the PMOS-driver control unit transmits an output signal of the fourth power-source level, upon receiving the third power-source-level small-amplitude input signal, and transmits an output signal of the first power-source level, upon receiving the fourth power-source-level small-amplitude input signal, and

the NMOS-driver control unit transmits an output signal of the third power-source level, upon receiving the fourth power-source-level small-amplitude input signal, and transmits an output signal of the second power-source level, upon receiving the third power-source-level small-amplitude input signal.

6. The level-conversion circuit according to claim 3 , wherein,

the PMOS-driver control unit comprises

i) a seventh transistor for transmitting the fourth power-source-level output signal,

ii) an eighth transistor for transmitting the first power-source-level output signal,

wherein when the fourth power-source-level output signal is transmitted, the eighth transistor is turned off, and when the first power-source-level output signal is transmitted, the seventh transistor is turned off, and

the NMOS-driver control unit comprises

i) a ninth transistor for transmitting the third power-source-level output signal,

ii) a tenth transistor for transmitting the second power-source-level output signal,

wherein when the third power-source-level output signal is transmitted, the tenth transistor is turned off, and when the second power-source-level output signal is transmitted, the ninth transistor is turned off.

7. The level-conversion circuit according to claim 3 , wherein,

the PMOS-driver control unit is separated from a first power source and the NMOS-driver control unit is separated from a second power source by using an activation signal.

8. The level-conversion circuit, comprising:

an output unit producing an output signal;

a power-source control unit connected between a power source line and the output unit; and

an output-feedback unit receiving the output signal and supplying a control signal to the power-source control unit,

wherein the power-source control unit supplies the output unit with a power voltage with a first current driving capability when the control signal takes a first level and with a second current driving capability when the control signal takes a second level, and

wherein the power-source control unit is a first power-source unit, the power-source line is a first power-source line, and the power voltage is a first power voltage,

the level-conversion circuit further comprising:

a second power-source control unit connected between a second power-source line and the output unit;

wherein the second power-source control unit supplies the output unit with a second power voltage with a third current driving capability when the control signal takes the first level and with a fourth current driving capability when the control signal takes the second level.

9. The level-conversion circuit according to claim 8 , wherein the first current driving capability is larger than the third current driving capability, and the second driving capability is smaller than the fourth current driving capability.

10. A level-conversion circuit, comprising:

first and second transistors connected in parallel to each other between a first power source and a first node;

third and fourth transistors connected in parallel to each other between a second power source and a second node;

a fifth transistor connected between the first node and an output node;

a sixth transistor connected between the second node and the output node;

a feedback unit connected to the output node and each of the first, second, third, and fourth transistors.

11. The level-conversion circuit according to claim 10 , wherein the feedback unit renders the first transistor active with the third transistor and the second transistor active with the fourth transistor.

12. The level-conversion circuit according to claim 11 , wherein the first transistor is larger in current driving capability than the third transistor, and the second transistor is smaller in current driving capability than the fourth transistor.