Testing apparatus and method which adjusts a phase difference between rising and falling signals output from a DUT
A test apparatus for testing a device under test includes a first timing comparator obtaining a device output signal output from the device under test at a timing designated by a first strobe signal, a second timing comparator obtaining the device output signal at a timing designated by a second strobe signal supplied later than the first strobe signal, a preceding edge judging circuit, when rising and falling signals are input at the same timing as the device output signal, judging which one of the rising and falling signals arrives at the first and second timing comparators at an earlier timing, a preceding edge detecting circuit adjusting a timing at which the first strobe signal is supplied so that the first timing comparator obtains, at a timing of a rising or falling edge, one of the rising and falling signals which is judged to arrive earlier, and a following edge detecting circuit adjusting a timing at which the second strobe signal is supplied so that the second timing comparator obtains, at a timing of a rising or falling edge, one of the rising and falling signals which is judged to arrive later.
1. A test apparatus for testing a device under test, comprising:
a first timing comparator that obtains a device output signal output from the device under test at a timing designated by a first strobe signal;
a second timing comparator that obtains the device output signal at a timing designated by a second strobe signal, the second strobe signal being supplied later than the first strobe signal;
a preceding edge judging circuit that, when a rising signal and a falling signal are input at the same timing as the device output signal, judges which one of the rising and falling signals arrives at the first and second timing comparators at an earlier timing;
a preceding edge detecting circuit that adjusts a timing at which the first strobe signal is supplied so that the first timing comparator obtains, at a timing of a rising or falling edge, one of the rising and falling signals which is judged to arrive earlier; and
a following edge detecting circuit that adjusts a timing at which the second strobe signal is supplied so that the second timing comparator obtains, at a timing of a rising or falling edge, one of the rising and falling signals which is judged to arrive later.
2. The test apparatus as set forth in claim 1 , further comprising:
a first variable delay circuit that outputs the first strobe signal which is generated by delaying a reference pulse signal;
a second variable delay circuit that outputs the second strobe signal which is generated by delaying the first strobe signal, wherein
the preceding edge detecting circuit adjusts a delay amount of the first variable delay circuit so that the first timing comparator obtains, at the timing of the rising or falling edge, one of the rising and falling signals which is judged to arrive earlier, and
the following edge detecting circuit adjusts a delay amount of the second variable delay circuit so that the second timing comparator obtains, at the timing of the rising or falling edge, one of the rising and falling signals which is judged to arrive later.
3. The test apparatus as set forth in claim 2 , further comprising:
an AND gate that outputs a logical AND between an output from the first timing comparator and an output from the second timing comparator;
an OR gate that outputs a logical OR between the output from the first timing comparator and the output from the second timing comparator; and
a comparison result selecting circuit that, as a timing comparison result which is obtained based on the device output signal during a test, (i) selects the output from the AND gate when the rising signal is judged to arrive earlier than the falling signal, and (ii) selects the output from the OR gate when the falling signal is judged to arrive earlier than the rising signal.
4. The test apparatus as set forth in claim 2 , wherein
the preceding edge detecting circuit causes one of the rising and falling signals which is judged to arrive earlier to be input as the device output signal for an adjustment use, and adjusts the delay amount of the first variable delay circuit so that the first timing comparator obtains the device output signal for an adjustment use at the timing of the rising or falling edge.
5. The test apparatus as set forth in claim 2 , wherein
the following edge detecting circuit causes one of the rising and falling signals which is judged to arrive later to be input as the device output signal for an adjustment use, and adjusts the delay amount of the second variable delay circuit so that the second timing comparator obtains the device output signal for an adjustment use at the timing of the rising or falling edge.
6. The test apparatus as set forth in claim 3 , further comprising:
a first selector that is connected so as to be positioned between the first timing comparator and the AND and OR gates, the first selector selecting to (i) input the output from the first timing comparator into the AND and OR gates or (ii) mask the output from the first timing comparator and input a signal indicating a logical value L into the AND and OR gates; and
a second selector that is connected so as to be positioned between the second timing comparator and the AND and OR gates, the second selector selecting to (I) input the output from the second timing comparator into the AND and OR gates or (II) mask the output from the second timing comparator and input a signal indicating a logical value L into the AND and OR gates.
7. The test apparatus as set forth in claim 6 , wherein
in such a state that the preceding edge detecting circuit causes the second selector to select the signal indicating the logical value L and causes the comparison result selecting circuit to select the output from the OR gate, the preceding edge detecting circuit adjusts the delay amount of the first variable delay circuit while one of the rising and falling signals which is judged to arrive earlier is input as the device output signal for an adjustment use, and
in such a state that the following edge detecting circuit causes the first selector to select the signal indicating the logical value L and causes the comparison result selecting circuit to select the output from the OR gate, the following edge detecting circuit adjusts the delay amount of the second variable delay circuit while one of the rising and falling signals which is judged to arrive later is input as the device output signal for an adjustment use.
8. The test apparatus as set forth in claim 6 , wherein
the preceding edge judging circuit includes:
an input control section that causes the device output signal to be input repeatedly while causing the second selector to mask the output from the second timing comparator and output the signal indicating the logical value L and causing the comparison result selecting circuit to select the output from the OR gate;
a first delay amount detecting section that, by causing the first timing comparator to sequentially obtain the rising signal which is repeatedly input while varying the delay amount of the first variable delay circuit, detects a first delay amount of the first variable delay circuit which enables the first timing comparator to obtain the rising signal at the timing of the rising edge;
a second delay amount detecting section that, by causing the first timing comparator to sequentially obtain the falling signal which is repeatedly input while varying the delay amount of the first variable delay circuit, detects a second delay amount of the first variable delay circuit which enables the first timing comparator to obtain the falling signal at the timing of the falling edge; and
a judging section that judges that the rising signal arrives earlier than the falling signal when the first delay amount is smaller than the second delay amount, and judges that the rising signal arrives later than the falling signal when the first delay amount is larger than the second delay amount.
9. The test apparatus as set forth in claim 8 , wherein
the delay amount of the first variable delay circuit is set by the preceding edge detecting circuit so as to be equal to a smaller one of the first and second delay amounts.
10. The test apparatus as set forth in claim 6 , wherein
wirings from the first and second timing comparators to the first and second selectors are longer than wirings from the first and second selectors to the AND and OR gates.
11. The test apparatus as set forth in claim 3 , further comprising:
a first selector that is connected so as to be positioned between the first timing comparator and the AND and OR gates, the first selector selecting to (i) input the output from the first timing comparator into the AND and OR gates or (ii) mask the output from the first timing comparator and input a signal indicating a logical value H into the AND and OR gates; and
a second selector that is connected so as to be positioned between the second timing comparator and the AND and OR gates, the second selector selecting to (I) input the output from the second timing comparator into the AND and OR gates or (II) mask the output from the second timing comparator and input a signal indicating a logical value H into the AND and OR gates.
12. The test apparatus as set forth in claim 11 , wherein
in such a state that the preceding edge detecting circuit causes the second selector to select the signal indicating the logical value H and causes the comparison result selecting circuit to select the output from the AND gate, the preceding edge detecting circuit adjusts the delay amount of the first variable delay circuit while one of the rising and falling signals which is judged to arrive earlier is input as the device output signal for an adjustment use, and
in such a state that the following edge detecting circuit causes the first selector to select the signal indicating the logical value H and causes the comparison result selecting circuit to select the output from the AND gate, the following edge detecting circuit adjusts the delay amount of the second variable delay circuit while one of the rising and falling signals which is judged to arrive later is input as the device output signal for an adjustment use.
13. A test method for testing a device under test, comprising:
obtaining a device output signal output from the device under test at a first timing designated by a first strobe signal;
obtaining the device output signal at a second timing designated by a second strobe signal, the second strobe signal being supplied later than the first strobe signal;
when a rising signal and a falling signal are input at the same timing as the device output signal, judging which one of the rising and falling signals arrives at the first and second timing comparators at an earlier timing;
adjusting the first timing designated by the first strobe signal so that one of the rising and falling signals which is judged to arrive earlier is obtained at a timing of a rising or falling edge; and
adjusting the second timing designated by the second strobe signal so that one of the rising and falling signals which is judged to arrive later is obtained at a timing of a rising or falling edge.