Semiconductor device
View Patent ↗A semiconductor device that can suppress noise transmission through a seal ring provided between two device regions. The semiconductor device includes a logic unit and an analog unit. The semiconductor device further includes a silicon substrate, an insulating interlayer, a seal ring surrounding the outer periphery of the logic unit composed of a conductive film buried in the insulating interlayer, a well provided on the silicon substrate, and an N well guard ring that blocks conduction of a path from the logic unit, through the seal ring to the analog unit. The N well guard ring is disposed between the seal ring region 106 and the logic unit or the analog unit.
1. A semiconductor device including a first device region and a second device region, said semiconductor device comprising:
a semiconductor substrate;
an insulating interlayer formed on said semiconductor substrate;
a seal ring composed of a conductive film buried in said insulating interlayer so as to surround an outer periphery of said first device region;
a blocking region composed of a well provided on said semiconductor substrate and blocking electric conduction in a path from said first device region to said second device region through said seal ring;
a first diffusion layer formed in an upper part of said semiconductor substrate and in contact with said seal ring; and
a second diffusion layer formed in contact with said first diffusion layer and covering said first diffusion layer,
wherein said second device region is disposed in one of an inside and an outside of said seal ring, and
wherein said blocking region is disposed between a seal ring region comprising said seal ring and one of said first device region and said second device region,
wherein said blocking region is electrically isolated,
wherein said blocking region is disposed between said second diffusion layer and said one of said first device region and said second device region,
wherein a conduction type of said second diffusion layer is opposite to a conduction type of said first diffusion layer, and
wherein said blocking region is a ring-like region surrounding a whole outer periphery of said one of said first device region and said second device region in a plan view.
2. The semiconductor device according to claim 1 ,
wherein said well forms a PN junction with a substrate region in said semiconductor substrate adjacent at a side surface of said well.
3. The semiconductor device according to claim 1 ,
wherein the conductive type of said well is N type.
4. The semiconductor device according to claim 3 ,
wherein said blocking region is composed of a plurality of ring-like N wells adjacent to each another through a P-type region.
5. The semiconductor device according to claim 4 ,
wherein each ring-like N well of said plurality of ring-like N wells has a plurality of chipped parts at which each of said plurality of ring-like N wells is divided, and
wherein said plurality of chipped parts are disposed as a staggered pattern.
6. The semiconductor device according to claim 3 ,
wherein said well is provided near a surface of said semiconductor substrate, and
wherein said blocking region includes a buried well connected to said well and provided immediately under said well.
7. The semiconductor device according to claim 2 ,
wherein said well is fixed at a predetermined potential.
8. The semiconductor device according to claim 1 ,
wherein said well has a same conductive type as a conductive type of an adjacent semiconductor region, and
wherein said well is fixed at a predetermined potential.
9. The semiconductor device according to claim 8 ,
wherein said well has a P conduction type.
10. The semiconductor device according to claim 1 ,
wherein said seal ring surrounds an outer periphery of said first device region and said second device region.
11. The semiconductor device according to claim 1 ,
wherein said blocking region is provided at a side of said seal ring and along said seal ring.
12. The semiconductor device according to claim 1 ,
wherein said seal ring is provided along a periphery of said semiconductor substrate, and
wherein said blocking region is provided inside said seal ring region and along said seal ring.
13. The semiconductor device according to claim 1 ,
wherein said blocking region does not overlap said seal ring region in a plan view.
14. The semiconductor device according to claim 1 , wherein both said first diffusion layer and said second diffusion layer are directly beneath said seal ring.