Semiconductor device and method for making the same
View Patent ↗In a MOS-type semiconductor device in which, on a Si substrate ( 201 ), a SiGe layer ( 202 ) having a valence band edge energy value smaller than a valence band edge energy value of the first semiconductor layer and a mobility larger than a mobility of the first semiconductor layer, a Si cap layer ( 203 ), and an insulating layer ( 204 ) are sequentially laminated, the problem of the shift of the absolute value of the threshold voltage toward a smaller value caused by negative fixed charges formed in or near the interface between the Si cap layer ( 203 ) and the insulting film ( 204 ) by diffusion of Ge is overcome by neutralizing the negative fixed charges by positive charges induced in and near the interface between the Si cap layer and the insulating film along with addition of nitrogen atoms to the semiconductor device surface by NO gas annealing and thereby shifting the threshold voltage toward a larger value.
1. A semiconductor device comprising:
a first semiconductor layer having an element region in which negative charges are introduced;
a second semiconductor layer having a valence band edge energy value smaller than a valence band edge energy value of the first semiconductor layer, and a mobility larger than a mobility of the first semiconductor layer, the second semiconductor layer being strained;
a third semiconductor layer having a valence band edge energy larger than the valence band edge energy of the second semiconductor layer, the third semiconductor layer being formed on the second semiconductor layer to form a heterojunction, and
an insulating layer,
wherein the first semiconductor layer, the second semiconductor layer, the third semiconductor layer and the insulating layer are sequentially stacked,
wherein a threshold voltage of a MOS transistor on the third semiconductor layer is controlled by an introduction of positive fixed charges introduced into and near an interface between the first semiconductor layer and the second semiconductor layer, an introduction of negative fixed charges into and near an interface between the second semiconductor layer and the third semiconductor layer and introduction of negative fixed charges into and near the interface between the third semiconductor layer and the insulating layer.
2. A semiconductor device according to claim 1 , wherein negative fixed charges introduced into and near an interface between the third semiconductor layer and the insulating layer are neutralized by introduction of positive fixed charges into and near the interface between the third semiconductor layer and the insulating layer.
3. A semiconductor device according to claim 1 , wherein a decrease in mobility is suppressed by introduction of negative fixed charges into and near an interface between the second semiconductor layer and the third semiconductor layer.
4. A semiconductor device comprising:
a first semiconductor layer having an element region in which negative charges are introduced;
a second semiconductor layer having a valence band edge energy value smaller than a valence band edge energy value of the first semiconductor layer, and a mobility larger than a mobility of the first semiconductor layer, the second semiconductor layer being strained;
a third semiconductor layer having a valence band edge energy larger than the valence band edge energy of the second semiconductor layer, the third semiconductor layer being formed on the second semiconductor layer to form a heterojunction;
an insulating layer; and
an element separation region in the first semiconductor layer, the element separation region defining the element region,
wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are sequentially stacked,
wherein a threshold voltage of a MOS transistor on the third semiconductor layer is controlled by introduction of positive fixed charges into and near an interface between the element region in the first semiconductor layer and the second semiconductor layer, introduction of negative fixed charges into and near an interface between the second semiconductor layer and the third semiconductor layer, introduction of positive fixed charges into and near an interface between the third semiconductor layer and the insulating layer, and controlling the total of the charges to a positive value and a decrease in mobility of the MOS transistor on the third semiconductor layer is suppressed by introduction of negative fixed charges into and near an interface between the second semiconductor layer and the third semiconductor layer, and
wherein a carrier region of the MOS transistor is present in the second semiconductor layer.
5. The semiconductor device according to claim 4 , wherein the negative fixed charges are introduced along with diffusion of an element constituting the second semiconductor layer, and the positive fixed charges are introduced along with addition of nitrogen atoms from outside.
6. The semiconductor device according to claim 5 , wherein the addition of nitrogen atoms is conducted through NO gas annealing.
7. The semiconductor device according to claim 5 , wherein the first semiconductor layer is Si, the second semiconductor layer is SiGe, the third semiconductor layer is Si, the element is Ge, and the insulating layer is silicon oxide.
8. The semiconductor device according to claim 7 , wherein the first semiconductor layer is n-type Si and the second semiconductor layer is n-type SiGe.
9. The semiconductor device according to claim 7 , wherein the first semiconductor layer is p-type Si and the second semiconductor layer is p-type SiGe.
10. The semiconductor device according to claim 4 , wherein the MOS transistor is a P type MOS transistor.