Post passivation interconnection schemes on top of IC chip
A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.
1 . A chip comprising:
a silicon substrate;
a first internal circuit in or on said silicon substrate;
a second internal circuit in or on said silicon substrate;
a dielectric layer over said silicon substrate;
a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit;
a first via in said dielectric layer and directly over said second internal circuit, wherein said first via is connected to said second internal circuit;
a passivation layer over said dielectric layer, wherein said passivation layer comprises nitride and oxide;
a second via in said passivation layer, wherein said second via is connected to said first interconnecting structure;
a third via in said passivation layer and directly over said first via, wherein said third via is connected to said first via; and
a second interconnecting structure over said passivation layer, wherein said second interconnecting structure is connected to said second and third vias, and wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said second via, said second interconnecting structure, said third via and said first via.
2 . The chip of claim 1 further comprising a third internal circuit in or on said silicon substrate, wherein said first interconnecting structure is connected to said third internal circuit, wherein said first internal circuit is connected to said third internal circuit through said first interconnecting structure, and wherein said third internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said second via, said second interconnecting structure, said third via and said first via.
3 . The chip of claim 1 , wherein said second interconnecting structure comprises a clock bus over said passivation layer, wherein said clock bus is connected to said second and third vias, and wherein said first internal circuit is connected to said second internal circuit through said clock bus.
4 . The chip of claim 1 , wherein said second interconnecting structure comprises a signal bus over said passivation layer, wherein said signal bus is connected to said second and third vias, and wherein said first internal circuit is connected to said second internal circuit through said signal bus.
5 . The chip of claim 1 , wherein said second interconnecting structure comprises a power bus over said passivation layer, wherein said power bus is connected to said second and third vias, and wherein said first internal circuit is connected to said second internal circuit through said power bus.
6 . The chip of claim 1 , wherein said second interconnecting structure comprises a ground bus over said passivation layer, wherein said ground bus is connected to said second and third vias, and wherein said first internal circuit is connected to said second internal circuit through said ground bus.
7 . The chip of claim 1 , wherein said second interconnecting structure comprises an interconnect line having a thickness greater than 1 micrometer.
8 . A chip comprising:
a silicon substrate;
a first internal circuit in or on said silicon substrate;
a second internal circuit in or on said silicon substrate;
a dielectric layer over said silicon substrate;
a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit;
a first via in said dielectric layer and directly over said second internal circuit, wherein said first via is connected to said second internal circuit;
a passivation layer over said dielectric layer;
a polymer layer over said passivation layer;
a second via in said polymer layer, wherein said second via is connected to said first interconnecting structure;
a third via in said polymer layer and directly over said first via, wherein said third via is connected to said first via; and
a second interconnecting structure in said polymer layer and over said passivation layer, wherein said second interconnecting structure is connected to said second and third vias, and wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said second via, said second interconnecting structure, said third via and said first via.
9 . The chip of claim 8 further comprising a third internal circuit in or on said silicon substrate, wherein said first interconnecting structure is connected to said third internal circuit, wherein said first internal circuit is connected to said third internal circuit through said first interconnecting structure, and wherein said third internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said second via, said second interconnecting structure, said third via and said first via.
10 . The chip of claim 8 , wherein said second interconnecting structure comprises a clock bus over said passivation layer and in said polymer layer, wherein said clock bus is connected to said second and third vias, and wherein said first internal circuit is connected to said second internal circuit through said clock bus.
11 . The chip of claim 8 , wherein said second interconnecting structure comprises a signal bus over said passivation layer and in said polymer layer, wherein said signal bus is connected to said second and third vias, and wherein said first internal circuit is connected to said second internal circuit through said signal bus.
12 . The chip of claim 8 , wherein said second interconnecting structure comprises a power bus over said passivation layer and in said polymer layer, wherein said power bus is connected to said second and third vias, and wherein said first internal circuit is connected to said second internal circuit through said power bus.
13 . The chip of claim 8 , wherein said second interconnecting structure comprises a ground bus over said passivation layer and in said polymer layer, wherein said ground bus is connected to said second and third vias, and wherein said first internal circuit is connected to said second internal circuit through said ground bus.
14 . The chip of claim 8 , wherein said second interconnecting structure comprises an interconnect line having a thickness greater than 1 micrometer.
15 . A chip comprising:
a silicon substrate;
a first internal circuit in or on said silicon substrate;
a second internal circuit in or on said silicon substrate;
a dielectric layer over said silicon substrate;
a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said first internal circuit;
a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said second internal circuit;
a passivation layer over said dielectric layer, wherein said passivation layer comprises nitride and oxide;
a polymer layer over said passivation layer;
a first via in said polymer layer, wherein said first via is connected to said first interconnecting structure;
a second via in said polymer layer, wherein said second via is connected to said second interconnecting structure; and
a third interconnecting structure over said passivation layer and in said polymer layer, wherein said third interconnecting structure is connected to said first and second vias, and wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure.
16 . The chip of claim 15 further comprising a third internal circuit in or on said silicon substrate, wherein said first interconnecting structure is connected to said third internal circuit, wherein said first internal circuit is connected to said third internal circuit through said first interconnecting structure, and wherein said third internal circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure.
17 . The chip of claim 15 , wherein said third interconnecting structure comprises a clock bus over said passivation layer and in said polymer layer, wherein said clock bus is connected to said first and second vias, and wherein said first internal circuit is connected to said second internal circuit through said clock bus.
18 . The chip of claim 15 , wherein said third interconnecting structure comprises a signal bus over said passivation layer and in said polymer layer, wherein said signal bus is connected to said first and second vias, and wherein said first internal circuit is connected to said second internal circuit through said signal bus.
19 . The chip of claim 15 , wherein said third interconnecting structure comprises a power bus over said passivation layer and in said polymer layer, wherein said power bus is connected to said first and second vias, and wherein said first internal circuit is connected to said second internal circuit through said power bus.
20 . The chip of claim 15 , wherein said third interconnecting structure comprises a ground bus over said passivation layer and in said polymer layer, wherein said ground bus is connected to said first and second vias, and wherein said first internal circuit is connected to said second internal circuit through said ground bus.