NAND-structured series variable-resistance material memories, processes of forming same, and methods of using same
View Patent ↗A variable-resistance material memory array includes a series of variable-resistance material memory cells. The series of variable-resistance material memory cells is in parallel with a corresponding series of control gates. A select gate is also in series with the variable-resistance material memory cells. Writing/reading/erasing to a given variable-resistance material memory cell includes turning off the corresponding control gate, while turning on all other control gates. Devices include the variable-resistance material memory array.
1. An apparatus comprising:
a plurality of n variable-resistance material memory (VRMM)cells connected in series above a semiconductive substrate, each VRMM cell coupled to two electrodes through spacer electrodes such that each spacer electrode contacts a lower film and an upper film;
a plurality of n corresponding control gates coupled in parallel to the plurality of n VRMM cells;
a select gate coupled in series to a first of the plurality of n VRMM cells; and
a bit line contact and a common source contact, wherein the bit line contact and the common source contact laterally encompass the plurality of n VRMM cells and the select gate.
2. The apparatus of claim 1 , wherein n is selected from 8, 16, 32, 64, or 128.
3. The apparatus of claim 1 , wherein the two spacer electrodes include doped polysilicon.
4. The apparatus of claim 1 , wherein each VRMM cell is coupled to circuitry through the spacer electrodes.
5. The apparatus of claim 1 , wherein wherein each of the two electrodes is coupled to the semiconductive substrate through an electrode contact.
6. The apparatus of claim 1 , wherein the common source contact is arrayed orthogonally to the plurality of n VRMM cells.
7. The apparatus of claim 1 , wherein the VRMM cell is a material selected from a metal, a metal alloy, a quasi-metal composition, a metal oxide, a chalcogenide, or combinations thereof.
8. The apparatus of claim 1 , wherein each VRMM cell includes material having a Perovskite structure.
9. The apparatus of claim 1 , wherein each VRMM cell includes a phase-change material composed of at least three elements such that one of the elements is present in the composition in an amount equal to or greater than 50 percent.
10. The apparatus of claim 1 , wherein the bit line contact is coupled to a global data bus.
11. A computing system, comprising:
a processor;
a memory apparatus coupled to the processor, wherein the memory apparatus includes:
a plurality of n variable-resistance material memory (VRMM)cells connected in series above a semiconductive substrate, each VRMM cell coupled to two electrodes through spacer electrodes such that each spacer electrode contacts a lower film and an upper film;
a plurality of n corresponding control gates coupled in parallel to the plurality of n VRMM cells;
a select gate coupled in series to a first of the plurality of n VRMM cells; and
a bit line contact and a common source contact, wherein the bit line contact and the common source contact laterally encompass the plurality of n VRMM cells and the select gate.
12. The computing system of claim 11 , wherein n is selected from 8, 16, 32, 64, or 128.
13. The computing system of claim 11 , wherein each VRMM cell includes a phase-change material.
14. The computing system of claim 11 , wherein each VRMM cell includes a magnetoresistive film.
15. The computing system of claim 11 , wherein the variable resistance memory material is selected from an alloy, a quasi-metal composition, a metal oxide, or a chalcogenide.
16. The apparatus of claim 11 , wherein the lower film includes a first dielectric and the upper film includes a second dielectric.