IP Library Granted Patent US 7,420,412
Granted Patent B2
US 7,420,412 · App. 11/857,923 · Granted Sep 2, 2008

Multiple power mode amplifier with bias modulation option and without bypass switches

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Quick Facts
Patent No.
US 7,420,412
App. No.
11/857,923
Granted
Sep 2, 2008
Kind
B2
Abstract

A multiple power mode amplifier provides a low and a high power mode without using switches. This amplifier may be used in radio frequency (RF) applications such as mobile telephones, pagers, portable digital assistants, and wireless e-mail devices. In the low power mode, the power consumption of the amplifier is reduced, which will increase operation time, especially important for battery-operated devices. In one implementation, the amplifier includes a number of impedance matching network units ( 130, 140, 150 , and 160 ), impedance transformer ( 170 ), and a power stage ( 120 ). An implementation provides further power consumption savings by modulating a bias of an amplifier stage.

Claims (23)

1. An integrated circuit comprising:

a first circuit branch, coupled between a first node and a second node, comprising a first amplifier stage and a second amplifier stage, coupled in series;

a second circuit branch, coupled between the second node and a third node, comprising a first impedance matching unit and a third amplifier stage, coupled in series; and

a third circuit branch, coupled between the second node and the third node, comprising an impedance transformer unit,

wherein during a first mode of operation of the circuit, the third amplifier stage is in an off state, consuming less power than in an on state, and a signal output from the first amplifier stage passes through the second amplifier stage and substantially through the third circuit branch, and

during a second mode of operation of the amplifier circuit, the third amplifier stage is in the on state and the signal output from the first amplifier stage passes through the second amplifier stage and substantially through the second circuit branch.

2. The integrated circuit of claim 1 wherein a gain of the first amplifier stage is variable.

3. The integrated circuit of claim 1 wherein a gain of the first amplifier stage is fixed.

4. The integrated circuit of claim 1 wherein the first amplifier stage comprises a predistorter circuit.

5. The integrated circuit of claim 1 wherein the first amplifier stage comprises a gain characteristic to compensate for nonlinearities in gain characteristics of the second and third amplifier stage.

6. The integrated circuit of claim 1 wherein a gain characteristic of the circuit, after passing through each of the first amplifier stage, second amplifier stage, and third amplifier stags, is more linear than the gain characteristic of the third amplifier stage.

7. The integrated circuit of claim 1 wherein the first circuit branch, second circuit branch, and third circuit branch are formed on a single semiconductor substrate.

8. The integrated circuit of claim 1 further comprising:

a voltage control circuit coupled to the third amplifier stage, wherein the voltage control circuit, in response to a mode control voltage, provides a control signal to the third amplifier stage to place the third amplifier stage in the on state or the off state.

9. The integrated circuit of claim 1 further comprising:

a voltage control circuit coupled to the first amplifier stage, second amplifier stage, and third amplifier stage, wherein the voltage control circuit, in response to a mode control voltage, provides a first signal to the first amplifier stage or the second amplifier stage to adjust a bias of the first amplifier stage or the second amplifier stage so during the first mode of operation the bias of the first amplifier stage or the second amplifier stage is reduced compared to the bias of the first amplifier stage or the second amplifier stage during the second mode of operation, and

the voltage control circuit, in response to the mode control voltage, provides a second signal to the third amplifier stage to place the third amplifier stage in the on state or the off state.

10. The integrated circuit of claim 1 further comprising:

a voltage control circuit coupled to each of the first amplifier stage, second amplifier stage, and third amplifier stage,

wherein the voltage control circuit, in response to a mode control voltage, provides a first signal to the first amplifier stage or the second amplifier stage to adjust a bias current of the first amplifier stage or the second amplifier stage so during the first mode of operation the bias current of the first amplifier stage or the second amplifier stage is reduced compared to the bias current of the first amplifier stage or the second amplifier stage during the second mode of operation, and

the voltage control circuit, in response to the mode control voltage, provides a second signal to the third amplifier stage to place the third amplifier stage in the on state or the off state.

11. The integrated circuit of claim 1 wherein the integrated circuit contains no bypass switches, wherein switches may include any of a relay, micromachined switch, transistor switch, PIN diode switch, or Schottky diode switch.

12. The integrated circuit of claim 1 wherein the first branch, second branch and third branch contain no bypass switches, wherein switches may include any of a relay, micromachined switch, transistor switch, PIN diode switch, or Schottky diode switch.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER PREVIOUSLY RECORDED AT REEL: 047357 FRAME: 0302. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048674/0834 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED ON REEL 047195 FRAME 0658. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047357/0302 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0658 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →