Multiple power mode amplifier with bias modulation option and without bypass switches
View Patent ↗A multiple power mode amplifier provides a low and a high power mode without using switches. This amplifier may be used in radio frequency (RF) applications such as mobile telephones, pagers, portable digital assistants, and wireless e-mail devices. In the low power mode, the power consumption of the amplifier is reduced, which will increase operation time, especially important for battery-operated devices. In one implementation, the amplifier includes a number of impedance matching network units ( 130, 140, 150 , and 160 ), impedance transformer ( 170 ), and a power stage ( 120 ). An implementation provides further power consumption savings by modulating a bias of an amplifier stage.
1. An integrated circuit comprising:
a first circuit branch, coupled between a first node and a second node, comprising N amplifier stages in series, wherein N is an integer 0 or greater,
a second circuit branch, coupled between the second node and a third node, comprising M amplifier stages in series, wherein M is an integer 1 or greater;
a voltage control circuit coupled to the least one amplifier stage of the M amplifier stages of the second branch, wherein the voltage control circuit, in response to a mode control voltage, provides a control signal to the least one amplifier stage of the M amplifier stages of the second branch to place the at least one amplifier stage of the M amplifier stages of the second branch in an on state or an off state; and
a third circuit branch, coupled between the second node and the third node, comprising an impedance transformer unit,
wherein during a first mode of operation of the circuit, at least one amplifier stage of the M amplifier stages of the second branch is in an off state, consuming less power than in an on state, and a signal output from the N amplifier stages of the first branch passes substantially through the third circuit branch, and
during a second mode of operation of the circuit, the M amplifier stages of the second circuit branch are in the on state and a signal output from N amplifier stages of the first branch passes substantially through the second circuit branch.
2. An integrated circuit comprising:
a first circuit branch, coupled between a first node and a second node, comprising N amplifier stages in series, wherein N is an integer 0 or greater,
a second circuit branch, coupled between the second node and a third node, comprising M amplifier stages in series, wherein M is an integer 1 or greater; and
a third circuit branch, coupled between the second node and the third node, comprising an impedance transformer unit,
wherein during a first mode of operation of the circuit, at least one amplifier stage of the M amplifier stages of the second branch is in an off state, consuming less power than in an on state, and a signal output from the N amplifier stages of the first branch passes substantially through the third circuit branch, and
during a second mode of operation of the circuit, the M amplifier stages of the second circuit branch are in the on state and a signal output from N amplifier stages of the first branch passes substantially through the second circuit branch; and
wherein a gain of at least one amplifier stage of the N amplifier stages of the first branch is variable.
3. The integrated circuit of claim 1 wherein a gain of at least one amplifier stage of the N amplifier stages of the first branch is fixed.
4. The integrated circuit of claim 2 wherein at least one amplifier stage of the N amplifier stages of the first branch comprises a predistorter circuit.
5. The integrated circuit of claim 2 wherein at least one amplifier stage of the N amplifier stages of the first branch comprises a gain characteristic to compensate for nonlinearities in a gain characteristic of at least one amplifier stage of M amplifier stages of the second branch.
6. The integrated circuit of claim 2 wherein a gain characteristic of the circuit, after passing through both the first branch and the second branch, is more linear than the gain characteristic of the second branch.
7. The integrated circuit of claim 1 wherein the first circuit branch, second circuit branch, and third circuit branch are formed on a single semiconductor substrate.
8. The integrated circuit of claim 2 further comprising
a voltage control circuit coupled to the least one amplifier stage of the M amplifier stages of the second branch, wherein the voltage control circuit, in response to a mode control voltage, provides a control signal to the least one amplifier stage of the M amplifier stages of the second branch to place the least one amplifier stage of the M amplifier stages of the second branch in an on state or an off state.
9. The integrated circuit of claim 2 further comprising:
a voltage control circuit coupled to at least one amplifier stage of the N amplifier stages of the first branch and the at least one amplifier stage of the M amplifier stages of the second branch,
wherein the voltage control circuit, in response to a mode control voltage, provides a first signal to the at least one amplifier stage of the N amplifier stages of the first branch to adjust a bias of the at least one amplifier stage of the N amplifier stages of the first branch so during the first mode of operation the bias of the at least one amplifier stage of the N amplifier stages of the first branch is reduced compared to the bias of the at least one amplifier stage of the N amplifier stages of the first branch during the second mode of operation, and
the voltage control circuit, in response to the mode control voltage, provides a second signal to the at least one amplifier stage of the M amplifier stages of the second branch to place the at least one amplifier stage of the M amplifier stages of the second branch in the on state or the off state.
10. The integrated circuit of claim 2 further comprising:
a voltage control circuit coupled to at least one amplifier stage of the N amplifier stages of the first branch and the at least one amplifier stage of the M amplifier stages of the second branch,
wherein the voltage control circuit, in response to a mode control voltage, provides a first signal to the at least one amplifier stage of the N amplifier stages of the first branch to adjust a bias current of the at least one amplifier stage of the N amplifier stages of the first branch so during the first mode of operation the bias current of the at least one amplifier stage of the N amplifier stages of the first branch is reduced compared to the bias current of the at least one amplifier stage of the N amplifier stages of the first branch during the second mode of operation, and
the voltage control circuit, in response to the mode control voltage, provides a second signal to the at least one amplifier stage of the M amplifier stages of the second branch to place the at least one amplifier stage of the M amplifier stages of the second branch in the on state or the off state.
11. The integrated circuit of claim 8 wherein the voltage control circuit comprises a transistor coupled between the least one amplifier stage of the M amplifier stages of the second branch and a reference voltage level, wherein an electrode of the transistor is coupled to a voltage control line.
12. The integrated circuit of claim 8 wherein the voltage control circuit comprises a transistor coupled between the least one amplifier stage of the M amplifier stages of the second branch and a reference voltage level and another transistor coupled between a supply voltage line and a reference voltage level, wherein an electrode of the former transistor is connected to the coupled point of the latter transistor toward the supply voltage line and an electrode of the latter transistor is coupled to a voltage control line.
13. The integrated circuit of claim 8 wherein the voltage control circuit comprises a transistor coupled between the least one amplifier stage of the M amplifier stages of the second branch and a reference voltage level and another transistor coupled between a supply voltage line and an electrode of the former transistor, wherein an electrode of the former transistor is coupled to the latter transistor and an electrode of the latter transistor is coupled to a voltage control line.
14. An integrated circuit comprising:
a first circuit branch, coupled between a first node and a second node, comprising N amplifier stages in series, wherein N is an integer 0 or greater,
a voltage control circuit coupled to the least one amplifier stage of the N amplifier stages of the first branch, wherein the voltage control circuit, in response to the mode control voltage, provides a signal to the least one amplifier stage of the N amplifier stages of the first branch to adjust a bias of the least one amplifier stage of the N amplifier stages of the first branch so during the first mode of operation the bias of the least one amplifier stage of the N amplifier stages of the first branch is reduced compared to the bias of the least one amplifier stage of the N amplifier stages of the first branch during the second mode of operation;
a second circuit branch, coupled between the second node and a third node, comprising M amplifier stages in series, wherein M is an integer 1 or greater; and
a third circuit branch, coupled between the second node and the third node, comprising an impedance transformer unit,
wherein during a first mode of operation of the circuit, at least one amplifier stage of the M amplifier stages of the second branch is in an off state, consuming less power than in an on state, and a signal output from the N amplifier stages of the first branch passes substantially through the third circuit branch, and
during a second mode of operation of the circuit, the M amplifier stages of the second circuit branch are in the on state and a signal output from N amplifier stages of the first branch passes substantially through the second circuit branch.
15. The integrated circuit of claim 14 wherein the voltage control circuit comprises a transistor coupled to the least one amplifier stage of the N amplifier stages of the first branch through a resistance and coupled to a reference voltage level though a resistance, wherein an electrode of the third transistor is coupled to a voltage control line.
16. The integrated circuit of claim 14 wherein the voltage control circuit comprises a transistor coupled to the least one amplifier stage of the N amplifier stages of the first branch and coupled to a reference voltage level though a resistance, wherein an electrode of the transistor is coupled to a voltage control line.
17. The integrated circuit of claim 14 wherein the voltage control circuit comprises a transistor coupled to the least one amplifier stage of the N amplifier stages of the first branch through a resistance and coupled to a reference voltage level, wherein an electrode of the transistor is coupled to a voltage control line.
18. The integrated circuit of claim 14 wherein the voltage control circuit comprises:
a transistor;
a resistance; and
one or more level shifting diodes, connected in series with the resistance,
wherein the resistance and the one or more level shifting diodes are coupled in series to the least one amplifier stage of the N amplifier stages of the first branch,
the transistor is coupled to the resistance and the one or more level shifting diodes and coupled to a reference voltage level, and
an electrode of the transistor is coupled to a voltage control line.
19. The integrated circuit of claim 2 wherein the integrated circuit contains no bypass switches, wherein switches may include any of a relay, micromachined switch, transistor switch, PIN diode switch, or Schottky diode switch.
20. The integrated circuit of claim 2 wherein the first branch, second branch and third branch contain no bypass switches, wherein switches may include any of a relay, micromachined switch, transistor switch, PIN diode switch, or Schottky diode switch.
21. The integrated circuit of claim 1 wherein N is 0, 1, 2, 3, 4, or 5.
22. The integrated circuit of claim 1 wherein M is 2, 3, 4, or 5.
23. The integrated circuit of claim 1 wherein N is 0, 1, 2, 3, 4, or 5, and M is 2, 3, 4, or 5.