Method and system for protecting data
Methods and systems for protecting data may include controlling encryption and/or decryption and identifying a destination of corresponding encrypted and/or decrypted data, utilizing rules based on a source location of the data prior to the encryption or decryption and an algorithm that may have been previously utilized for encrypting and/or decrypting the data prior to the data being stored in the source location. The source location and/or destination of the data may comprise protected or unprotected memory. One or more of a plurality of algorithms may be utilized for the encryption and/or decryption. The rules may be stored in a key table, which may be stored on-chip, and may be reprogrammable. One or more keys for the encryption and/or decryption may be generated within the chip.
1. A method for data communication, the method comprising:
in a security processor on a chip, controlling encryption and/or decryption of data and identifying a destination of corresponding encrypted and/or decrypted data utilizing one or more rules based on:
a source location of said data prior to said encryption and/or decryption; and
an algorithm that was previously utilized for encrypting and/or decrypting said data prior to said data being stored in said source location.
2. The method according to claim 1 , wherein said source location of said data comprises protected memory.
3. The method according to claim 1 , wherein said source location of said data comprises unprotected memory.
4. The method according to claim 1 , wherein said destination of said data comprises protected memory.
5. The method according to claim 1 , wherein said destination of said data comprises unprotected memory.
6. The method according to claim 1 , comprising utilizing one or more of a plurality of algorithms for each of said encryption and/or decryption.
7. The method according to claim 1 , comprising storing said rules in a key table.
8. The method according to claim 7 , comprising storing said key table on said chip.
9. The method according to claim 7 , comprising storing said key table in one-time-programmable memory on said chip.
10. The method according to claim 7 , wherein said key table is reprogrammable.
11. The method according to claim 1 , comprising generating one or more keys for said encryption and/or decryption within said chip.
12. A system for data communication, the system comprising:
one or more circuits within a security processor on a chip that enable controlling encryption and/or decryption of data and identifying a destination of corresponding encrypted and/or decrypted data utilizing one or more rules based on:
a source location of said data prior to said encryption and/or decryption; and
an algorithm that was previously utilized for encrypting and/or decrypting said data prior to said data being stored in said source location.
13. The system according to claim 12 , wherein said source location of said data comprises protected memory.
14. The system according to claim 12 , wherein said source location of said data comprises unprotected memory.
15. The system according to claim 12 , wherein said destination of said data comprises protected memory.
16. The system according to claim 12 , wherein said destination of said data comprises unprotected memory.
17. The system according to claim 12 , wherein said one or more circuits enable utilizing one or more of a plurality of algorithms for each of said encryption and/or decryption.
18. The system according to claim 12 , wherein said one or more circuits enable storing said rules in a key table.
19. The system according to claim 18 , wherein said one or more circuits enable storing said key table on said chip.
20. The system according to claim 18 , comprising storing said key table in one-time-programmable memory on said chip.
21. The system according to claim 18 , wherein said one or more circuits enable reprogramming said key table.
22. The system according to claim 12 , wherein said one or more circuits enable generating one or more keys for said encryption and/or decryption within said chip.
23. A machine-readable storage having stored thereon, a computer program having at least one code section for data communication, the at least one code section being executable by a machine for causing the machine to perform steps comprising:
in a security processor on a chip, controlling encryption and/or decryption of data and identifying a destination of corresponding encrypted and/or decrypted data utilizing one or more rules based on:
a source location of said data prior to said encryption and/or decryption; and
an algorithm that was previously utilized for encrypting and/or decrypting said data prior to said data being stored in said source location.
24. The machine readable storage according to claim 23 , wherein said source location of said data comprises protected memory.
25. The machine readable storage according to claim 23 , wherein said source location of said data comprises unprotected memory.
26. The machine readable storage according to claim 23 , wherein said destination of said data comprises protected memory.
27. The machine readable storage according to claim 23 , wherein said destination of said data comprises unprotected memory.
28. The machine readable storage according to claim 23 , wherein said at least one code section comprises code for utilizing one or more of a plurality of algorithms for each of said encryption and/or decryption.
29. The machine readable storage according to claim 23 , wherein said at least one code section comprises code for storing said rules in a key table.
30. The machine readable storage according to claim 29 , wherein said at least one code section comprises code for storing said key table on said chip.
31. The machine readable storage according to claim 29 , wherein said at least one code section comprises code for storing said key table in one-time-programmable memory on said chip.
32. The machine readable storage according to claim 29 , wherein said at least one code section comprises code for reprogramming said key table.
33. The machine readable storage according to claim 23 , wherein said at least one code section comprises code for generating one or more keys for said encryption and/or decryption within said chip.