Electrically erasable programmable read-only memory cell and memory device and manufacturing method thereof
View Patent ↗A manufacturing method and a device of an EEPROM cell are provided. The method includes the following steps. First, a tunnel layer and an inter-gate dielectric layer are formed over a surface of a substrate respectively, and a doped region is formed in the substrate under the inter-gate dielectric layer and used as a control gate. Thereafter, a floating gate is formed over the inter-gate dielectric layer and the tunnel layer. Thereafter, a source region and a drain region are formed in the substrate beside two sides of the floating gate under the tunnel layer. Especially, the manufacturing method of the memory cell can be integrated with the manufacturing process of high operation voltage component and low operation voltage component.
1. A memory device, comprising:
a substrate comprising a memory cell area and a peripheral circuit area, wherein the peripheral circuit area comprises a high operational voltage component area and a low operational voltage component area;
at least a memory cell, disposed in the memory cell area, wherein each of the memory cell comprises:
an inter-gate dielectric layer and a tunnel layer, disposed over a surface of the substrate of the memory cell area respectively;
a doped region, disposed in the substrate under the inter-gate dielectric layer, and used as a control gate;
a floating gate, disposed over the tunnel layer and the inter-gate dielectric layer; and
a first source region and a first drain region, disposed in the substrate of two sides of the floating gate under the tunnel layer;
at least a high operational voltage component, disposed in the high operational voltage component area, wherein each of the high operational voltage component comprises:
a first inter-gate dielectric layer, disposed over a surface of the substrate of the high operational voltage component area;
a first gate, disposed over the first inter-gate dielectric layer; and
a second source region and a second drain region, disposed in the substrate of two sides of the first gate; and
at least a low operational voltage component, disposed in the low operational voltage component area, wherein each of the low operational voltage component comprises;
a second inter-gate dielectric layer, disposed over a surface of the substrate of the low operational voltage component area;
a second gate, disposed over the second inter-gate dielectric layer; and
a third source region and a third drain region, disposed in the substrate of two sides of the second gate.
2. The device of claim 1 , wherein a thickness of the inter-gate dielectric layer is greater than a thickness of the tunnel layer.
3. The device of claim 1 , wherein a thickness of the first inter-gate dielectric layer is greater than a thickness of the second inter-gate dielectric layer.
4. The device of claim 1 , further comprises:
a deeply doped region, disposed in the substrate under the tunnel layer of the memory cell area, wherein the first source region is disposed in the deeply doped region.
5. The device of claim 1 , further comprises:
a deeply doped region, correspondingly disposed in the substrate of two sides of the first gate of the high operational voltage component area, wherein the second source region and the second drain region are disposed in the deeply doped region.
6. The device of claim 1 , further comprises:
a first well region and a second well region, disposed in the substrate of the memory cell area, wherein the tunnel layer is disposed over a surface of the first well region, and the inter-gate dielectric layer is disposed over a surface of the second well region, and the doped region used as the control gate is form in the second well region.