Semiconductor integrated circuit device having a decoupling capacitor
View Patent ↗The bottom side of an N type silicon substrate is connected to a power supply terminal, a second P type epitaxial layer is formed on all sides of the N type silicon substrate, and a device forming portion is provided on the second P type epitaxial layer. A first P type epitaxial layer and an interlayer insulating film are provided on the device forming portion and an N well and a P well are formed on the top surface of the first P type epitaxial layer. The second P type epitaxial layer is connected to a ground terminal via the first P type epitaxial layer, the P well, a p + diffusion region, a via and a wire. Accordingly, a pn junction is formed at the interface between the second P type epitaxial layer and the N type silicon substrate.
1. A semiconductor integrated circuit device comprising:
a first conductivity type semiconductor substrate;
a first conductivity type semiconductor layer provided on said first conductivity semiconductor substrate, said first conductivity type semiconductor layer being coupled to a first power supply;
a device forming portion provided on an upper surface of said first conductivity type semiconductor layer and including a second conductivity type well connected to a second power supply, and a first conductivity type well, wherein the entirety of said device forming portion is provided on the upper surface of said first conductivity type semiconductor layer, said device forming portion having a bottom surface contacting with said upper surface of said first conductivity type semiconductor layer, said upper surface of said first conductivity type semiconductor layer being substantially flat, and wherein a first device is formed within a region of the device forming ortion including the first conductivity type well and a second device is formed within a region of the device forming portion including the second conductivity type well; and
a decoupling capacitor formed at an interface between said first conductivity type semiconductor layer and said second conductivity type well.
2. The semiconductor integrated circuit device according to claim 1 , wherein said first conductivity type semiconductor layer is connected to said first power supply via said first conductivity type semiconductor substrate.
3. The semiconductor integrated circuit device according to claim 1 , wherein said device forming portion has an active element connected to third and fourth power supplies, and a potential of said third power supply differs from potentials of said first and second power supplies.
4. The semiconductor integrated circuit device according to claim 1 , wherein said first conductivity type semiconductor layer is provided on an entire top surface of said first conductivity type semiconductor substrate.
5. The semiconductor integrated circuit device according to claim 1 , wherein said first conductivity type semiconductor layer is connected to said first power supply via said first conductivity type well.