Data line disturbance free memory block divided flash memory and microcomputer having flash memory therein
View Patent ↗A semiconductor device having an electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.
1. A data processing apparatus packaged in one package, comprising:
a central processing unit; and
a flash memory,
wherein the central processing unit has a first mode and a second mode:
in the first mode, the central processing unit is in a low consumption mode; and
in the second mode, the central processing unit is capable of programming data into the flash memory, and
wherein the flash memory is capable of being programmed data, under control by an apparatus external of the data processing apparatus, when the central processing unit is in the first mode.
2. A data processing apparatus according to claim 1 ,
wherein in the second mode, the central processing unit performs a first program for programming data to the flash memory fetched from a random access memory, and
wherein the first program is transferred from the flash memory to the random access memory before performing the first program.
3. A data processing apparatus according to claim 2 ,
wherein the flash memory contains a plurality of erase blocks, and
wherein the first program is programmed in one erase block, which is a different block than a block to be programmed data by the central processing unit in the second mode, by the external apparatus in the first mode.
4. A data processing apparatus according to claim 3 ,
wherein a second program for transferring the first program from the one erase block of the flash memory to the random access memory is programmed into the flash memory before performing of the first program, and
wherein the central processing unit performs the second program for transferring the first program from the flash memory to the random access memory before performing the first program.
5. A data processing apparatus, contained in a single package, comprising:
a central processing unit provided with at least a first mode and a second mode; and
a flash memory,
wherein the central processing unit functions such that:
in the first mode, the central processing unit is in a low power consumption state; and
in the second mode, the central processing unit is enabled for programming data into the flash memory, and
wherein the flash memory is adapted for programming data therein which is under external control of the data processing apparatus, when the central processing unit is in the first mode.
6. A data processing apparatus according to claim 5 ,
wherein in the second mode, the central processing unit performs a first program for programming data to the flash memory fetched from a random access memory, and
wherein the first program is transferred from the flash memory to the random access memory before performing the first program.
7. A data processing apparatus according to claim 6 ,
wherein the flash memory contains a plurality of erase blocks, and
wherein the first program is programmed in one erase block, which is a different block than a block to be programmed data by the central processing unit in the second mode, by an external apparatus in the first mode.
8. A data processing apparatus according to claim 7 ,
wherein a second program for transferring the first program from the one erase block of the flash memory to the random access memory is programmed into the flash memory before performing of the first program, and
wherein the central processing unit performs the second program for transferring the first program from the flash memory to the random access memory before performing the first program.