Integrated circuit having a memory with process-voltage-temperature control
View Patent ↗Certain embodiments of the inventions provide an integrated circuit (IC) having a processor operatively coupled to a PVT (process-voltage-temperature) source and an adjustable memory. The processor receives from the source an input characterizing the present PVT condition and generates a command for the memory based on that input. In response to the command, the memory adjusts its internal circuit structure, clock speed, and/or operating voltage(s) to optimize its performance for the present PVT condition. Advantageously, the ability to adjust the memory so that it can maintain its functionality and deliver an acceptable level of performance under unfavorable PVT conditions provides additional flexibility in choosing circuit design options, which can produce area savings and/or increase the yield of acceptable ICs during manufacture.
1. An integrated circuit (IC), comprising:
a source adapted to characterize one or more of process, voltage, and temperature conditions of the IC;
a processor operatively coupled to the source and adapted to receive from the source an input providing the one or more characterized conditions; and
a memory operatively coupled to the processor and adapted to be adjusted in response to a command from the processor, said command being generated based on the one or more characterized conditions, wherein:
the memory is adapted to adjust its effective circuit structure in response to said command;
said structure adjustment comprises an inclusion or exclusion of a transistor module of a modular transistor;
the modular transistor comprises a first transistor module and a second transistor module connected in parallel to one another so that a gate of the first transistor module and a gate of the second transistor module are both connected to a signal-input terminal;
the IC comprises a first programmable switch configured between the first transistor module and the second transistor module to controllably engage or disengage the second transistor module with the first transistor module, said first programmable switch being controlled in response to the command;
in a first state of the first programmable switch, a signal-output terminal of the modular transistor is connected to the first transistor module but not the second transistor module; and
in a second state of the first programmable switch, the signal-output terminal of the modular transistor is connected to both the first transistor module and the second transistor module.
2. The invention of claim 1 , wherein:
said structure adjustment further comprises an adjustment of a timing path;
the IC comprises a second programmable switch configured between the timing path and a capacitor, said second programmable switch being controlled in response to the command;
in a first state of the second programmable switch, the capacitor is coupled to the timing path;
in a second state of the second programmable switch, the capacitor is decoupled from the timing path; and
the coupling and decoupling of the capacitor changes signal propagation time through the timing path.
3. The invention of claim 1 , wherein the memory comprises:
an array of memory cells organized in rows and columns, wherein each row is connected to a respective row line and each column is connected to a respective bit line;
a plurality of row drivers, each adapted to activate a respective row line;
a plurality of sense amplifiers, each adapted to latch a signal onto or from a respective bit line; and
a control circuit adapted to change, in response to said command, a delay time between activation of a selected row driver and latching of the sense amplifiers.
4. The invention of claim 1 , wherein:
the processor is further adapted to receive an input specifying chip-requirement information;
the chip-requirement information includes one or more of a clock speed, a time constraint for a task to be run by the IC, a mode of operation, and one or more values for voltages generated by a charge pump or a voltage regulator that is part of the IC; and
said command is generated based on the chip-requirement information.
5. The invention of claim 4 , wherein the processor is adapted to generate said command to optimize operation of the memory for the one or more provided conditions and the chip-requirement information.
6. The invention of claim 5 , wherein said optimization comprises optimization of power consumption.
7. The invention of claim 1 , wherein the source comprises a sensor adapted to sense the one or more of process, voltage, and temperature conditions.
8. The invention of claim 1 , wherein the processor is a shared processor that is further adapted to perform power control and speed stepping.
9. The invention of claim 1 , wherein the processor is a shared processor that is further adapted to perform data processing.
10. The invention of claim 1 , wherein the source comprises memory storage elements adapted to provide the process conditions.
11. The invention of claim 10 , wherein the process conditions include transistor characteristics.
12. The invention of claim 10 , wherein the process conditions include digital circuit speed performance.
13. The invention of claim 1 , wherein the first transistor module and the second transistor module are parts of a modular inverter.
14. A method of operating an integrated circuit (IC), comprising:
characterizing one or more of process, voltage, and temperature conditions of the IC with a source, wherein the IC comprises:
the source;
a processor operatively coupled to the source and adapted to receive from the source an input providing the one or more characterized conditions; and
a memory operatively coupled to the processor;
generating, using the processor, a command for the memory based on the one or more characterized conditions; and
adjusting the memory in response to said command, wherein:
the step of adjusting comprises adjusting an effective circuit structure of the memory in response to said command; and
said structure adjustment comprises an inclusion or exclusion of a transistor module of a modular transistor;
the modular transistor comprises a first transistor module and a second transistor module connected in parallel to one another so that a gate of the first transistor module and a gate of the second transistor module are both connected to a signal-input terminal;
the IC comprises a first programmable switch configured between the first transistor module and the second transistor module to controllably engage or disengage the second transistor module with the first transistor module, said first programmable switch being controlled in response to the command;
in a first state of the first programmable switch, a signal-output terminal of the modular transistor is connected to the first transistor module but not the second transistor module; and
in a second state of the first programmable switch, the signal-output terminal of the modular transistor is connected to both the first transistor module and the second transistor module.
15. The invention of claim 14 , wherein:
said structure adjustment further comprises an adjustment of a timing path;
the IC comprises a second programmable switch configured between the timing path and a capacitor, said second programmable switch being controlled in response to the command;
in a first state of the second programmable switch, the capacitor is coupled to the timing path;
in a second state of the second programmable switch, the capacitor is decoupled from the timing path; and
the coupling and decoupling of the capacitor changes signal propagation time through the timing path.
16. The invention of claim 14 , wherein the first transistor module and the second transistor module are parts of a modular inverter.