Metal wiring of semiconductor device and forming method thereof
View Patent ↗A metal wiring of a semiconductor device and a forming method thereof are provided. A dielectric layer is formed on a semiconductor substrate including a lower metal wiring. A SOG (spin on glass) coating layer is formed on the dielectric layer to inhibit material from another layer from infiltrating into the dielectric layer.
1. A method of forming a metal wiring of a semiconductor device, comprising:
providing a semiconductor substrate including a lower metal wiring;
forming a dielectric layer on the semiconductor substrate and exposing the lower metal wiring through a via hole;
forming a spin on glass (SOG) coating layer on the dielectric layer including in the via hole;
forming a barrier metal layer on the SOG coating layer and the lower metal wiring; and
forming an upper metal wiring on the barrier metal layer, electrically connected to the lower metal wiring;
wherein the dielectric layer comprises a first dielectric layer and a second dielectric layer, and wherein the method further comprises:
forming a first etch stop layer below the first dielectric layer; and
forming a second etch stop layer on the first dielectric layer and below the second dielectric layer.
2. The method according to claim 1 , wherein forming the upper metal wiring comprises:
forming a seed layer on the barrier metal layer; and
performing an electroplating process.
3. The method according to claim 1 , comprising:
forming the first etch stop layer on the semiconductor substrate and the lower metal wiring;
forming the first dielectric layer on the first etch stop layer;
forming the second etch stop layer on the first dielectric layer;
forming the second dielectric layer on the second etch stop layer; and
forming the via hole and a trench above the via hole exposing the lower metal wiring.
4. The method according to claim 3 , wherein forming the via hole and the trench comprises:
forming the via hole by etching through the second dielectric layer, the second etch stop layer, the first dielectric layer, and the first etch stop layer; and
forming the trench by etching through the second dielectric layer and the second etch stop layer.
5. The method according to claim 3 , wherein forming the SOG coating layer comprises covering the sidewalls of the trench and via hole.
6. The method according to claim 1 , wherein the dielectric layer comprises a porous material.
7. The method according to claim 1 , wherein the dielectric layer comprises a material with a dielectric constant of about 1.1 to about 2.4.
8. The method according to claim 1 , wherein the SOG coating layer has low dielectric properties.
9. The method according to claim 1 , wherein the barrier metal layer comprises Ta, TaN, or TaSiN.
10. The method according to claim 1 , further comprising removing a portion of the SOG coating layer to expose the lower metal wiring before forming the barrier metal layer.