IP Library Granted Patent US 8,119,424
Granted Patent B2
US 8,119,424 · App. 11/864,409 · Granted Feb 21, 2012

Electronic device including a magneto-resistive memory device and a process for forming the electronic device

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Quick Facts
Patent No.
US 8,119,424
App. No.
11/864,409
Granted
Feb 21, 2012
Kind
B2
Abstract

A process of forming an electronic device can include forming a stack including a tunnel barrier layer. The tunnel barrier layer can have a ratio of the metal atoms to oxygen atoms of greater than a stoichiometric ratio, wherein the ratio has a particular value. The process can also include forming a gettering layer having a composition capable of gettering oxygen, and depositing an insulating layer over the gettering layer. The process can further include exposing the insulating layer to a temperature of at least approximately 60° C. In one embodiment, after such exposure, a portion of the gettering layer is converted to an insulating material. In another embodiment, an electronic device can include a magnetic tunnel junction and an adjacent insulating layer lying within an opening in another insulating layer.

Claims (37)

1. A process of manufacturing an electronic device comprising:

forming a first conductive layer over a substrate;

forming a magneto-resistive random access memory cell stack over the first conductive layer, wherein forming the magneto-resistive random access memory cell stack includes:

forming a first magnetic layer in electrical contact with the first conductive layer;

forming a tunnel barrier layer over the first magnetic layer;

forming a second magnetic layer over the tunnel barrier layer; and

forming a second conductive layer in electrical contact with the second magnetic layer;

etching a portion of the second magnetic layer to expose a portion of the tunnel barrier layer,

forming a metal layer over the exposed portion of the tunnel barrier layer; and

forming an insulating layer on the metal layer wherein the tunnel barrier and the insulating layer are separated by the metal layer,

wherein, during or subsequent to forming the insulating layer, at least a portion of the metal layer disposed on the exposed portion of the tunnel barrier layer is converted into an insulating material.

2. The process of claim 1 , wherein:

forming the first magnetic layer includes forming a fixed layer, wherein the fixed layer has a magnetization fixed in a particular orientation; and

forming the second magnetic layer includes forming a free layer, wherein the free layer has a magnetization in any one of a plurality of orientations.

3. The process of claim 1 , wherein forming the tunnel barrier layer includes:

forming a metal layer including magnesium, aluminum, titanium, hafnium, zirconium, tantalum, or any combination thereof.

4. The process of claim 1 , wherein:

forming the tunnel barrier layer and etching a portion of the second magnetic layer includes forming the tunnel barrier layer having a first active area and a resistance-area product of not greater than approximately 100 Ω-μm 2 as deposited; and

after annealing the substrate, the tunnel barrier layer has a second active area, wherein a difference between the first active area and the second active area is not more than approximately 10 percent.

5. The process of claim 1 , further including removing an oxygen-containing material from the magneto-resistive random access memory cell stack prior to forming the metal layer.

6. The process of claim 1 further comprising:

exposing the stack to a temperature higher than 60° C., wherein after exposing the stack, a portion of the metal layer is converted to an insulating material.

7. The process of claim 1 wherein the etching step further comprises:

forming an edge of the second conductive layer and the second magnetic layer; and

the forming a metal layer further comprises:

forming the metal layer on the edge.

8. The process of claim 1 wherein the forming a metal layer further comprises:

forming the metal layer over the second conductive layer; and

further comprising after the forming an insulating layer:

removing the metal layer over the second conductive layer.

9. The process of claim 1 wherein the etching step further comprises:

etching the tunnel barrier layer and the first magnetic layer to expose the first conductive layer to form an edge of the second conductive layer, the second magnetic layer, the tunnel barrier layer, the first magnetic layer; and the forming a metal layer comprises forming on the edge and on the first conductive layer.

10. The process of claim 1 wherein forming the metal layer comprises forming a metal layer having a thickness in the range of 1.0 to 10.0 nm.

11. The process of claim 1 wherein the forming the metal layer comprises depositing at an incident angle to the substrate.

12. The process of claim 1 wherein the tunnel barrier layer and the metal layer comprise the same metal.

13. The process of claim 1 wherein the insulating layer is selected from the group consisting of an oxide, a nitride, an oxynitride, or a combination thereof.

14. The process of claim 5 wherein the removing an oxygen-containing material consists of sputtering.

Assignments (14)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
PATENT RELEASE Recorded Aug 17, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 039707/0471 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0704 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2015
From: FREESCALE SEMICONDUCTOR, INC.
To: EVERSPIN TECHNOLOGIES, INC.
Reel/Frame 036084/0057 →
RELEASE OF SECURITY INTEREST Recorded Jul 30, 2010
From: CITIBANK, N.A.
To: EVERSPIN TECHNOLOGIES, INC.
Reel/Frame 024767/0398 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2009
From: FREESCALE SEMICONDUCTOR, INC.
To: EVERSPIN TECHNOLOGIES, INC.
Reel/Frame 022366/0467 →