IP Library › Granted Patent US 7,643,331
Granted Patent B2
US 7,643,331 · App. 11/866,144 · Granted Jan 5, 2010

Semiconductor device

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 7,643,331
App. No.
11/866,144
Granted
Jan 5, 2010
Kind
B2
Abstract

In one aspect of the present invention, a semiconductor device A semiconductor device may include a SRAM cell having a first inverter, a second inverter, a first transfer transistor and a second transistor, the first inverter having a first load transistor and a first driver transistor connected to the first load transistor, the second inverter having a second load transistor and a second driver transistor connected to the second load transistor, a voltage supplying circuit configured to supply a voltage to one of the terminals of the first driver transistor and one of the terminals of the second driver transistor, the voltage which is one of more than a GND voltage and less than a GND voltage.

Claims (8)

1. A semiconductor device, comprising:

a SRAM cell having a first inverter, a second inverter, a first transfer transistor and a second transfer transistor, the first inverter having a first load transistor and a first driver transistor connected to the first load transistor, the second inverter having a second load transistor and a second driver transistor connected to the second load transistor,

a voltage supplying circuit configured to supply a voltage to one of the terminals of the first driver transistor and one of the terminals of the second driver transistor, the voltage which is one of more than a GND voltage and less than a GND voltage,

wherein the voltage supplying circuit supplies a voltage which is less than a GND voltage to the terminal of the first driver transistor and the terminal of the second driver transistor when data is started to be written to the SRAM cell.

2. A semiconductor device of claim 1 , wherein transistors provided in the SRAM cell are Fin transistors, respectively, and a gate length and fin width of the transistors are substantially same.

3. A semiconductor device of claim 1 , wherein the first transfer transistor, the second transfer transistor, the first driver transistor and the second driver transistor are Fin transistors.

4. A semiconductor device of claim 1 , wherein the voltage supplying circuit is configured to supply a voltage which is equal to or more than a GND voltage to the terminal of the first driver transistor and the terminal of the second driver transistor, after finishing writing of data to the SRAM cell.

5. A semiconductor device of claim 1 , wherein the voltage supplying circuit is configured to supply a voltage which is equal to or more than a GND voltage to the terminal of the first driver transistor and the terminal of the second driver transistor, after finishing writing of data to the SRAM cell.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2007
From: INABA, SATOSHI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 020111/0075 →
Priority Claims (1)
JP 2006-272081 · Oct 3, 2006 · national
Continuity (1)
Related Publication 20080253170A1 · Oct 16, 2008