DRAM and SRAM mixedly mounted semiconductor device
View Patent ↗A semiconductor device in which a DRAM and a SRAM are mixedly mounted is provided. The DRAM and the SRAM have a stack-type structure in which a bitline is formed below a capacitive element. A cross couple connection of the SRAM is formed in a layer or below the layer in which a capacitive lower electrode of the DRAM is formed and in a layer or above the layer in which the bitline is formed. For example, the cross couple connection of the SRAM is formed in a same layer as a capacitive contact.
1. A semiconductor device, comprising: a substrate having a first region, a second region and a third region, a DRAM formed in the first region,
an SRAM formed in the second region, said SRAM including two access transistors,
gate electrodes of said access transistors being separated from each other, a logic formed in the third region, a first wiring layer which comprises a lowest metal layer, a first insulating layer formed on the first wiring layer, a second wiring layer formed on the first insulating layer, a second insulating layer formed on the second wiring layer, and a third wiring layer formed on the second insulating layer,
wherein said SRAM is connected to said first and second wiring layers, but not said third wiring layer, and
whereby intermacro connections between the DRAM, logic and SRAM need not bypass the second region containing the SRAM;
wherein said DRAM cell is formed on a substrate, said DRAM cell having a transistor connecting to a bit line and capacitor having a lower electrode, a dielectric film and an upper electrode; and
said SRAM cell is formed on the substrate, said SRAM cell having a cross couple connection;
wherein said cross couple connection is formed in a layer formed between said dielectric film and a layer of a plug which connects to said bit line.
2. The semiconductor device according to claim 1 , wherein said cross couple connection of the SRAM cell is in the same layer as said bit line of the DRAM cell.
3. The semiconductor device according to claim 2 , wherein a resistance of the cross couple connection of the SRAM cell is higher than a resistance of a metal wiring used above the upper electrode of the DRAM cell.
4. The semiconductor device according to claim 2 , wherein the DRAM cell has a stack-type structure.
5. The semiconductor device according to claim 1 , wherein said cross couple connection of the SRAM cell is in the same layer as a plug contact which connects to the lower electrode of the capacitance of the DRAM cell.
6. The semiconductor device according to claim 5 , wherein a resistance of the cross couple connection of the SRAM cell is higher than a resistance of a metal wiring used above the upper electrode of the DRAM cell.
7. The semiconductor device according to claim 5 , wherein the DRAM cell has a stack-type structure.
8. The semiconductor device according to claim 1 , wherein said cross couple connection of the SRAM cell is in the same layer as the lower electrode of the capacitance of the DRAM cell.
9. The semiconductor device according to claim 8 , wherein a resistance of the cross couple connection of the SRAM cell is higher than a resistance of a metal wiring used above the upper electrode of the DRAM cell.
10. The semiconductor device according to claim 8 , wherein the DRAM cell has a stack-type structure.
11. The semiconductor device according to claim 1 , wherein a resistance of the cross couple connection of the SRAM cell is higher than a resistance of a metal wiring used above the upper electrode of the DRAM cell.
12. The semiconductor device according to claim 1 , wherein the DRAM cell has a stack-type structure.
13. The semiconductor device according to claim 1 , wherein said third wiring layer is formed over said SRAM, and said third wiring layer is above the most upper layer of the SRAM.
14. The semiconductor device according to claim 1 , wherein said DRAM and said logic are connected to one or more of said first wiring layer, said second wiring layer, and said third wiring layer.
15. The semiconductor device according to claim 1 , further including wiring for selectively interconnecting said DRAM, said logic, and said SRAM, wherein said wiring for selectively interconnecting said DRAM, said logic, and said SRAM is located in part in said second region and forming a portion of said third wiring layer.
16. The semiconductor device according to claim 1 , wherein DRAM is connected to only said first wiring layer and said logic is connected to said first wiring layer, said second wiring layer, and said third wiring layer.