Nano-electronic memory array

1. A memory device, comprising:

an array of memory cells disposed in rows and columns and constructed over a substrate, each memory cell comprising a first signal electrode, a second signal electrode, and a nano-layer disposed in the intersecting region between the first signal electrode and the second signal electrode;

a plurality of word lines each connecting the first signal electrodes of a row of memory cells; and

a plurality of bit lines each connecting the second signal electrodes of a column of memory cells, wherein the nano-layer comprises optical nano elements.

2. The memory device of claim 1 , wherein the optical nano elements are spin coated above the second layer.

3. The memory device of claim 1 , further comprising a driver circuit for selectively controlling the first signal electrodes or the second signal electrodes.

4. The memory device of claim 3 , wherein the circuit includes one or more of a Y gate, a sense amplifier, an input-output buffer, an X address decoder, a Y address decoder, and an address buffer.

5. The memory device of claim 1 , wherein the substrate includes a silicon-on-insulator wafer.

6. The memory device of claim 1 , wherein the nano-optical layer is spin-coated over the substrate where the first signal electrodes and the second signal electrodes are constructed.

7. The memory device of claim 1 , further comprising an array of redundant nano elements.

8. The memory device of claim 7 , wherein the redundant array is a row or a column of redundant nano-elements.

9. The memory device of claim 1 , further comprising memory devices forming a plurality of memory hierarchy to optimize data access speed.

10. The memory device of claim 1 , further comprising a programmable logic nano-element coupled to the memory cell.

11. A memory electronic device, comprising:

a substrate;

a first layer fabricated using semiconductor fabrication techniques;

a second layer formed above the first layer, the second layer having one or more nano-bonding areas;

one or more nano memory elements self-assembled to the second layer molecular bonding areas, wherein the nano-laver comprises optical nano elements.

12. The memory device of claim 11 , wherein the optical nano elements are spin coated above the second layer.

13. The memory device of claim 11 , further comprising a driver circuit for selectively controlling the first signal electrodes or the second signal electrodes.

14. The memory device of claim 13 , wherein the circuit includes one or more of a Y gate, a sense amplifier, an input-output buffer, an X address decoder, a Y address decoder, and an address buffer.

15. The memory device of claim 11 , wherein the nano-optical layer is spin-coated over the substrate where the first signal electrodes and the second signal electrodes are constructed.

16. The memory device of claim 11 , further comprising an array of redundant nano elements.

17. The memory device of claim 11 , further comprising memory devices forming a plurality of memory hierarchy to optimize data access speed.

18. The memory device of claim 11 , further comprising a programmable logic nano-element coupled to the memory cell.

19. A method to process a semiconductor substrate, comprising:

fabricating a first layer on the substrate using semiconductor fabrication techniques;

fabricating a second layer above the first layer having one or more nano-bonding areas; and

self-assemblying one or more optical nano memory-elements; and

bonding the memory nano elements to the bonding areas.

20. The method of claim 19 , wherein the optical nano-elements are spin-coated on the second layer.