Partitioned Integrated Circuit Package with Central Clock Driver
Disclosed are IC partitioned packaging and interconnection constructions that provide for improved distribution of power, ground, cross chip interconnections and clocks.
1 . An integrated circuit (IC) package assembly comprising:
at least one IC die interconnected to a first interconnection redistribution substrate, said substrate having planar dimensions less than the IC die to form a subassembly, the subassembly being interconnected to a second interconnection redistribution substrate having dimensions greater than the subassembly, and wherein both subassembly and the IC package assembly have independent interconnection.
2 . An integrated circuit (IC) package assembly comprising
a first semiconductor die;
a second semiconductor die including a clock driver circuit; and
a clock signal distribution structure coupled between the clock driver circuit and the first semiconductor die.
3 . The IC package assembly of claim 2 wherein the clock driver circuit is configured to output multiple clock signals that are delivered via the clock signal distribution structure to respective points on the semiconductor die.
4 . The IC package assembly of claim 3 wherein the clock signal distribution structure comprises a plurality of signal paths each to conduct a respective one of the multiple clock signals, wherein each signal path of at least a subset of the plurality of signal paths has substantially the same length as each other signal path of the subset.
5 . The IC package assembly of claim 3 wherein the second semiconductor provides at least one of the clock signals distributed from clock driver and additional signals are of different lengths.
6 . The IC package assembly of claim 3 wherein the second semiconductor die is disposed at a location offset from the center of the IC package assembly and wherein at least one of the multiple clock signals is fed into or near the center of the IC package assembly and are distributed to separate clock signals of the substrate and each signal trace has the same length.
7 . The IC package assembly of claim 3 wherein the second semiconductor is offset from the center of IC package assembly and wherein the multiple clock signals are fed into a central region of the IC package assembly and are distributed to one or more clock signal rings.
8 . The IC package assembly of claim 3 wherein the clock driver circuit comprises programmable circuitry to enable adjustment of the phase of at least one of the multiple clock signals.
9 . The IC package assembly of claim 2 wherein the clock driver circuit comprises an input to receive a reference clock signal from the first semiconductor die.
10 . The IC package assembly of claim 2 wherein the clock driver circuit comprises an input to receive a reference clock signal from a source external to the IC package assembly.