Power mosfet including inter-source connection pattern
View Patent ↗A power metal oxide silicon field effect transistor in which sources are connected to each other, a single source supplies electrons to two channels, a contact surface between the source and a channel is variously changed to be maximized such that large current flows in a small area, and an electrical field is not concentrated to a gate edge.
1. An apparatus comprising:
a semiconductor substrate;
a plurality of gates provided over the semiconductor substrate;
a plurality of body regions forming an array over the semiconductor substrate and adjacent the plurality of gates; and
a plurality of inter-source connection patterns surrounding and extending between adjacent body regions for supplying current to the plurality of gates, wherein the inter-source connection patterns have a predetermined geometric pattern extending to a contact area of the plurality of gates,
wherein the gates have chamfers such that an angle at corners of the gates are prevented from changing abruptly.
2. The apparatus of claim 1 , wherein a portion of the inter-source connection patterns extending between adjacent body regions includes a first extension portion extending linearly between adjacent body regions and a second extension portion extending substantially perpendicular from the first extension portion in a direction toward the plurality of gates.
3. The apparatus of claim 2 , wherein each distal end of the second extension portion has a substantially rectangular shape.
4. The apparatus of claim 1 , wherein a portion of the inter-source connection patterns extending between adjacent body regions includes a first linear extension portion extending linearly between adjacent body regions and at least two parallel extension portions extending substantially perpendicular from the first extension portion in a direction toward the plurality of gates.
5. The apparatus of claim 4 , wherein each distal end of the at least parallel extension portions has a substantially rectangular shape.
6. The apparatus of claim 1 , wherein the plurality of inter-source connection patterns are formed of n+-type dopants.
7. An apparatus comprising:
a semiconductor substrate;
a plurality of gates provided over the semiconductor substrate;
a plurality of body regions forming an array over the semiconductor substrate and adjacent the plurality of gates; and
a plurality of inter-source connection patterns surrounding and extending between adjacent body regions for supplying current to the plurality of gates, wherein the inter-source connection patterns have a predetermined geometric pattern extending to a contact area of the plurality of gates,
wherein a portion of the inter-source connection patterns extending between adjacent body regions includes a first extension portion extending linearly between adjacent body regions and a second extension portion extending substantially perpendicular from the first extension portion in a direction toward the plurality of gates, and
wherein each distal end of the second extension portion has a substantially triangular shape.
8. An apparatus comprising:
a semiconductor substrate;
a plurality of gates provided over the semiconductor substrate;
a plurality of body regions forming an array over the semiconductor substrate and adjacent the plurality of gates; and
a plurality of inter-source connection patterns surrounding and extending between adjacent body regions for supplying current to the plurality of gates, wherein a portion of the inter-source connection patterns extending between adjacent body regions includes a first linear extension portion extending linearly between adjacent body regions and at least two parallel extension portions extending substantially perpendicular from the first extension portion in a direction toward the plurality of gates,
wherein the gates have chamfers such that an angle at corners of the gates are prevented from changing abruptly.