Method of packaging and interconnection of integrated circuits
View Patent ↗A method is disclosed for packaging semiconductor chips on a flexible substrate employing thin film transfer. The semiconductor chips are placed on a temporary adhesive substrate, then covered by a permanent flexible substrate with a casting layer for planarizingly embedding the chips on the permanent substrate before removing the temporary substrate. With the surface of the chips coplanar with the surface of the complete structure without any gaps, interconnect metal lines can be easily placed on the uninterrupted surface, connecting the chips and other components.
1. A coplanar, gapless semiconductor chip packaging structure comprising a plurality of semiconductor chips embedded in a substrate through a curable layer, the curable layer covering an entire top surface of the substrate,
wherein each of the chips comprises a plurality of exposed contact pads on a top surface thereof, having respective top surface being coplanar with the top surface of each of the chips;
wherein the top surface of each of the chips is coplanar with a top surface of the curable layer and there is no gap at the sides of each of the chips, forming a planar, uninterrupted surface, and a plurality of interconnect lines connecting the exposed contact pads, wherein the curable layer entirely covers all sides and a bottom of each of the chips.
2. A structure as in claim 1 wherein the curable layer has a coefficient of thermal expansion similar to that of silicon.
3. A structure as in claim 1 wherein the curable layer partially covers the bottom of the semiconductor chips.
4. A structure as in claim 1 wherein the interconnect lines connecting the top exposed contact pads are planar.
5. A structure as in claim 1 wherein the curable layer is disposed on the chips before applying the substrate.
6. A structure as in claim 1 wherein the curable layer completely covers the chips and the substrate so that the substrate surface is not exposed.
7. A structure as in claim 1 wherein the curable layer covers only the sides of the chips.
8. A flexible chip packaging structure comprising
a flexible substrate;
a plurality of semiconductor chips embedded in the flexible substrate through a curable layer covering an entire top surface of the substrate,
wherein each of the semiconductor chips comprises a plurality of exposed contact pads on a top surface thereof, having respective top surface being coplanar with the top surface of each of the semiconductor chips;
wherein the top surface of each of the semiconductor chips is coplanar with a top surface of the curable layer and there is no gap at the sides of each of the semiconductor chips, forming a planar, uninterrupted surface, and a plurality of interconnect lines connecting the exposed contact pads, wherein the curable layer entirely covers all sides and a bottom of each of the semiconductor chips.
9. A structure as in claim 8 wherein the curable layer has a coefficient of thermal expansion similar to that of silicon.
10. A structure as in claim 8 wherein the interconnect lines connecting the top exposed contact pads are planar.
11. A structure as in claim 8 wherein the curable layer is disposed on the chips before applying the substrate.
12. A structure as in claim 8 wherein the curable layer completely covers the chips and the substrate so that the substrate surface is not exposed.
13. A structure as in claim 8 wherein the curable layer covers only the sides of the chips.
14. A structure as in claim 8 wherein the curable layer partially covers the bottom of the semiconductor chips.
15. A semiconductor structure comprising:
a plurality of semiconductor chips embedded in a substrate through a curable layer, the curable layer covering an entire top surface of the substrate,
wherein each of the semiconductor chips comprises a plurality of exposed contact pads on a top surface thereof, having respective top surface being coplanar with the top surface of each of the semiconductor chips, and
wherein the top surface of each of the semiconductor chips is coplanar with a top surface of the curable layer and there is no gap at the sides of each of the semiconductor chips, forming a planar, uninterrupted surface; and
a plurality of planar interconnect lines connecting the exposed contact pads, wherein the curable layer entirely covers all sides and a bottom of each of the semiconductor chips.
16. A structure as in claim 15 wherein the curable layer completely covers the semiconductor chips and the substrate so that the substrate surface is not exposed.
17. A structure as in claim 15 wherein the curable layer covers only the sides of the semiconductor chips.
18. A structure as in claim 15 wherein the curable layer partially covers the bottom of the semiconductor chips.