Ternary content addressable memory with block encoding
View Patent ↗The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.
1. A semiconductor device comprising an input/output circuit arranged to connect a first group of signal lines and a second group of signal lines, a first register, an encoder, an entry compressor and a memory array, wherein
the input/output circuit outputs a first information or a second information to the second group of signal lines,
the first register holds the first information,
the encoder outputs a third information encoded based on the first and second information received through the second group of signal lines to a third group of signal lines,
the entry compressor receives a plurality of the third information sequentially inputted through the third group of signal lines and performs logical operation to generate a fourth information and outputs the fourth information to a fourth group of signal lines, and
the memory array stores the fourth information inputted through the fourth group of signal lines and compares the fourth information with the third information through the third group of signal lines.
2. The semiconductor device according to claim 1 , wherein the encoder encodes in units of the plurality of bits.
3. The semiconductor device according to claim 2 , wherein the entry compressor includes a first plurality of registers, a comparator and an OR circuit, wherein
the first plurality of registers store a plurality of the third information,
the comparator compares the information stored in each of the plurality of first registers per bit, and
the OR circuit performs logical sum of the information stored in each of the plurality of registers per bit according to the result of comparison by the comparator to generate the fourth information.
4. The semiconductor device according to claim 3 , wherein the semiconductor device further comprises a second register and a third register, a decoder, and an entry extractor, wherein
the entry extractor divides the fourth information read from the memory array through the fourth group of signal lines to generate a fifth plurality of information and stores the plurality of information,
the decoder stores the plurality of first and second information obtained by decoding each of the fifth plurality of information received through a fifth group of signal lines,
the second register stores a plurality of the first information received through the fifth group of signal lines,
the third register stores a plurality of the second information received through the fifth group of signal lines, and
a plurality of the first information stored in the second register and a plurality of the second information stored in the third register are outputted from the second group of signal lines to the first group of signal lines through the input/output circuit.
5. The semiconductor device according to claim 4 , wherein the semiconductor device further comprises a counter and a memory array comprised of dynamic memory cells, wherein
the counter generates a row address to select the plurality of memory cells in refresh operations.