Level converter and semiconductor device

1. A level converter, comprising:

a first to fourth transistors formed of a semiconductor having a same conductivity type; and

a resistance connected between first and second output terminals,

wherein the first transistor is connected between a first power supply and the second output terminal,

wherein the second transistor is connected between a second power supply and the first output terminal,

wherein the third transistor is connected between the first power supply and the first output terminal,

wherein the fourth transistor is connected between the second power supply and the second output terminal,

wherein the first and the second transistors are input with one of first differential signals, and

wherein the third and the fourth transistors are input with another of the first differential signals.

2. The level converter according to claim 1 , further comprising an inductor connected between the first and the second output terminals.

3. The level converter according to claim 1 , further comprising a resistance and an inductor connected between the first and the second output terminals.

4. The level converter according to claim 1 , wherein the level converter outputs a second differential signal, the second differential signal being the first differential signal with signal level shifted.

5. The level converter according to claim 4 , wherein the first and the second differential signals are CML level signals having a smaller amplitude than a potential difference between the first and second power supplies.

6. The level converter according to claim 4 , wherein an amplitude and a signal level of the second differential signal output from the first output terminal is configured according to a ratio between resistance values generated in the second and the third transistors, and

wherein an amplitude and a signal level of the second differential signal output from the second output terminal is configured according to a ratio between resistance values generated in the first and the fourth transistors.

7. The level convener according to claim 1 , wherein the second transistor comprises a source connected to a second power supply and a drain connected to a first output terminal.

8. The level convener according to claim 1 , wherein the fourth transistor comprises a source connected to the second power supply and a drain connected to the second output terminal.

9. A level converter, comprising:

a first to fourth transistors formed of a semiconductor having a same conductivity type;

a resistance connected between the first and the second output terminals;

a first source follower including the first transistor having a source connected to a first power supply and a drain connected to the second output terminal and the fourth transistor having a drain connected to a second power supply and a source connected to the second output terminal; and

a second source follower including the third transistor having a source connected to the first power supply and a drain connected to the first output terminal and the second transistor having a drain connected to the second power supply and a source connected to the first output terminal,

wherein one of first differential signals is input to the first and the second transistors, and

wherein another of the first differential signals is input to the third and the fourth transistors.

10. The level convener according to claim 9 , further comprising an inductor connected between the first and the second output terminals.

11. The level convener according to claim 9 , further comprising a resistance and an inductor connected between the first and the second output terminals.

12. The level converter according to claim 9 , wherein the level converter outputs a second differential signal, the second differential signal being the first differential signal with signal level shifted.

13. The level converter according to claim 12 , wherein the first and the second differential signals are CML level signals having a smaller amplitude than a potential difference between the first and second power supplies.

14. The level converter according to claim 9 , wherein the resistance comprises a first resistor and a second resistor, and

wherein an inductance is provided in series with the first resistor and the second resistor.

15. The level converter according to claim 9 , further comprising a frequency characteristic adjusting circuit provided between the first and the second output terminals, the frequency characteristic adjusting circuit comprising an inductance.

16. The level converter according to claim 9 , further comprising a frequency characteristic adjusting circuit provided between the first and the second output terminals, the frequency characteristic adjusting circuit comprising a resistance.

17. The level converter according to claim 9 , wherein the first to fourth transistors comprise N-Channel Metal Oxide Semiconductor (NMOS) Transistors.

18. A semiconductor device, comprising:

a first level convener to convert a differential input signal into a first differential signal having a first signal level;

a second level converter to convert a differential input signal into a second differential signal having a second signal level; and

a third level convener to convert the first differential signal into the second differential signal,

wherein the third level converter is connected between the first level converter and the second level convener.

19. The semiconductor device according to claim 18 , wherein the third level converter emphasizes a frequency component near a cutoff frequency of the first differential signal.

20. The semiconductor device according to claim 18 , wherein the differential input signal and the first and the second differential signals have a smaller amplitude than a potential difference between a first and a second power supplies.