Granted Patent B2

US 7,419,864 · App. 11/882,355 · Granted Sep 2, 2008

Abstract

Claims (51)

1. A method of manufacturing a semiconductor device, comprising the steps of:

forming an element isolation insulating film, which defines first and second low-voltage transistor forming regions and first and second high-voltage transistor forming regions, on a semiconductor substrate;

forming a first gate insulating film on the semiconductor substrate in the first and second high-voltage transistor forming regions;

forming a second gate insulating film on the semiconductor substrate in the first and second low-voltage transistor forming regions;

forming an undoped conductive film on the first and second gate insulating films;

implanting selectively a first conductivity type impurity into the conductive film in the first low-voltage transistor forming region and the first and second high-voltage transistor forming regions;

patterning the conductive film after the first conductivity type impurity is implanted, to form first and second gate electrodes in the first and second low-voltage transistor forming regions respectively and form third and fourth gate electrodes in the first and second high-voltage transistor forming regions respectively;

forming selectively first and second source/drain extensions of first conductivity type on the semiconductor substrate beside the first and third gate electrodes respectively;

forming selectively third and fourth source/drain extensions of second conductivity type, which is opposite to the first conductivity type, on the semiconductor substrate beside the second and fourth gate electrodes respectively;

forming first to fourth insulating sidewalls beside the first to fourth gate electrodes respectively;

forming low-voltage first conductivity type source/drain region away from side surfaces of the first gate electrode at a first interval after the first to fourth insulating sidewalls are formed, and forming high-voltage first conductivity type source/drain region away from side surfaces of the third gate electrode at a second interval that is wider than the first interval;

forming low-voltage second conductivity type source/drain region away from side surfaces of the second gate electrode at the first interval after the first to fourth insulating sidewalls are formed, and forming high-voltage second conductivity type source/drain region away from side surfaces of the fourth gate electrode at the third interval that is wider than the first interval; and

introducing a second conductivity type impurity into the second gate electrode.

2. A method of manufacturing a semiconductor device, according to claim 1 , wherein the step of forming the first to fourth insulating sidewalls includes the steps of,

forming a sidewall insulating film, which covers the first to fourth gate electrodes, in the first and second low-voltage transistor forming regions and the first and second high-voltage transistor forming regions,

forming first and second openings in the sidewall insulating film and the first gate insulating film away from side surfaces of the third and fourth gate electrodes at the second and third interval respectively, and making the sidewall insulating film left on an upper surfaces and sides of the third and fourth gate electrode into the third and the fourth insulating sidewalls, and

etching the third and fourth insulating sidewalls on upper surfaces of the third and fourth gate electrodes to expose the third and fourth gate electrodes except edges of the upper surfaces thereof, and etching back the sidewall insulating film in the first and second low-voltage transistor forming regions to leave the film as the first and second insulating sidewalls beside the first and second gate electrodes.

3. A method of manufacturing a semiconductor device, according to claim 2 , wherein the step of forming the high-voltage first and second conductivity type source/drain regions is executed by implanting a first conductivity type impurity into the silicon substrate via the first opening and implanting a second conductivity type impurity into the silicon substrate via the second opening.

4. A method of manufacturing a semiconductor device, according to claim 3 , further comprising the step of:

forming a silicide layer on upper surfaces of the first and second gate electrodes and upper surfaces of the third and fourth gate electrodes except the edge portions after the first and second insulating sidewalls are formed.

5. A method of manufacturing a semiconductor device, according to claim 1 , wherein the first gate insulating film is formed thicker than the second gate insulating film, in the step of forming the first gate insulating film.

6. A method of manufacturing a semiconductor device, according to claim 1 , wherein the step of forming the first to fourth insulating sidewalls includes the steps of,

forming a sidewall insulating film, which covers the first to fourth gate electrodes, in the first and second low-voltage transistor forming regions and the first and second high-voltage transistor forming regions, and

etching back the sidewall insulating film by an etching depth, at which an etching residue of the first gate insulating film is left, to make the sidewall insulating film left beside the first to fourth gate electrodes into the first to fourth insulating sidewall,

and the method further comprising the step of:

forming third and fourth openings in portions of the first gate insulating film, which are away from side surfaces of the third and fourth gate electrodes at the second interval respectively, before the step of forming the high-voltage first and second conductivity type source/drain regions; and

wherein the step of forming the high-voltage first and second conductivity type source/drain regions is executed by implanting a first conductivity type impurity into the silicon substrate via the third opening and implanting a second conductivity type impurity into the silicon substrate via the fourth opening.

7. A method of manufacturing a semiconductor device, according to claim 6 , further comprising the steps of:

forming an interlayer insulating film to cover the first to fourth gate electrodes after the low-voltage first and second conductivity type source/drain regions and the high-voltage first and second conductivity type source/drain regions are formed;

patterning the interlayer insulating film to form first and second holes on the low-voltage first and second conductivity type source/drain regions respectively and form third and fourth holes on the high-voltage first and second conductivity type source/drain regions respectively; and

forming first to fourth conductive plugs in the first to fourth holes.

8. A method of manufacturing a semiconductor device, according to claim 7 , wherein, in the step of forming the interlayer insulating film, the interlayer insulating film is formed by stacking an etching stopper film and an insulating film in this order, and

in the step of forming the first to fourth holes, the first to fourth holes are formed by etching the insulating film under the condition where the etching is stopped on the etching stopper film, and then etching the etching stopper film.

9. A method of manufacturing a semiconductor device, comprising the steps of:

forming an element isolation insulating film, which defines first and second low-voltage transistor forming regions and first and second high-voltage transistor forming regions, on a semiconductor substrate;

forming a first gate insulating film on the semiconductor substrate in the first and second high-voltage transistor forming regions;

forming a second gate insulating film, which is thinner than the first gate insulating film, on the semiconductor substrate in the first and second low-voltage transistor forming regions;

forming an undoped conductive film on the first and second gate insulating films;

patterning the conductive film to form first and second gate electrodes in the first and second low-voltage transistor forming regions respectively and form third and fourth gate electrodes in the first and second high-voltage transistor forming regions respectively;

forming a sidewall insulating film in the first and second low-voltage transistor forming regions and the first and second high-voltage transistor forming regions to cover the first to fourth gate electrodes;

removing the sidewall insulating film from upper surfaces of the first to fourth gate electrodes by etching back the sidewall insulating film by an etching depth at which an etching residue of the first gate insulating film is left, and making the sidewall insulating film left beside the first to fourth gate electrode into first to fourth insulating sidewalls;

forming a first opening in the first gate insulating film away from a side surface of the third insulating sidewall at an interval, and forming a second opening in the first gate insulating film away from a side surface of the fourth insulating sidewall at an interval;

introducing a first conductivity type impurity into the first gate electrode, as well as forming low-voltage first conductivity type source/drain region on the silicon substrate beside the first gate electrode, and forming high-voltage first conductivity type source/drain region on the silicon substrate under the first opening;

introducing a second conductivity type impurity into the second gate electrode, as well as forming low-voltage second conductivity type source/drain region on the silicon substrate beside the second gate electrode, and forming high-voltage second conductivity type source/drain region on the silicon substrate under the second opening;

introducing the impurity into all portions of the third gate electrode; and

introducing the impurity into all portions of the fourth gate electrode.

10. A method of manufacturing a semiconductor device, according to claim 9 , further comprising the step of:

forming a silicide layer on overall upper surfaces of at least the third and fourth gate electrodes.

11. A method of manufacturing a semiconductor device, according to claim 9 , wherein, in the step of forming the first insulating film, a thickness of the first insulating film is set such that the thickness is able to block the first conductivity type impurity used in the step of forming the high-voltage first conductivity type source/drain region or the second conductivity type impurity used in the step of forming the high-voltage second conductivity type source/drain region.

12. A method of manufacturing a semiconductor device, according to claim 9 , wherein the first conductivity type impurity is introduced into the third gate electrode, in the step of introducing the impurity into the third gate electrode, and

the first conductivity type impurity is introduced into the fourth gate electrode, in the step of introducing the impurity into the fourth gate electrode.

Assignments (8)