Semiconductor integrated circuit device having latchup preventing function
View Patent ↗Latchup is prevented from occurring accompanying increasingly finer geometries of a chip. NchMOSFET N 1 and PchMOSFET P 1 form a CMOS circuit including: NchMOSFET N 2 whose gate, drain and back gate are connected to back gate of N 1 and PchMOSFET P 2 whose gate, drain and back gate are connected to back gate of P 1 . Source of N 2 is connected to source of N 1 . Source of P 2 is connected to source of P 1 . N 2 is always connected between the grounded source of N 1 and the back gate of N 1 , while P 2 is connected between source of P 1 connected to a power supply and the back gate of P 1 . Each of N 2 and P 2 functions as a voltage limiting element (a limiter circuit).
1. A semiconductor integrated circuit device, comprising:
a CMOS circuit that comprises:
a well region of a first conductivity type formed in a band form in a substrate;
a well region of a second conductivity type formed in a band form in said substrate, said well region of the second conductivity type being arranged in parallel with and adjacent to said well region of the first conductivity type;
a first diffusion region of the first conductivity type formed in said well region of the first conductivity type and connected to a first back bias supplying power supply line that supplies a back bias to be supplied to said well region of the first conductivity type;
first and second power supply lines that supply power to said CMOS circuit; and
a MOSFET of the second conductivity type formed in said well of the first conductivity type, a gate and a drain of the MOSFET of the second conductivity type being connected to the well region of the first conductivity type through a second diffusion region of the first conductivity type formed in the well region which is not connected to the first back bias supplying power supply line, and a source of the MOSFET of the second conductivity type being connected to the first power supply line.
2. The semiconductor integrated circuit device according to claim 1 , wherein a plurality of the first diffusion regions of the first conductivity type are present in said well region of the first conductivity type, and the second diffusion region of the first conductivity type is arranged generally in the middle of two of said first diffusion regions of the first conductivity type, said second diffusion region of the first conductivity type serving as a connecting spot between the drain of said MOSFET of the second conductivity type and the well region of the first conductivity type.
3. The semiconductor integrated circuit device according to claim 2 , wherein a drain region of said MOSFET of the second conductivity type and said second diffusion region of the first conductivity type are formed, adjacent to each other, in said well region of the first conductivity type.
4. The semiconductor integrated circuit device according to claim 1 , further comprising:
a plurality of cells each formed over said well region of the first conductivity type and said well region of the second conductivity type;
at least one portion of each of said cells including said MOSFET of the second conductivity type and the second diffusion region of the first conductivity type, said second diffusion region of the first conductivity type serving as a connecting spot between the drain of the MOSFET of the second conductivity type and said well region of the first conductivity type.
5. The semiconductor integrated circuit device according to claim 4 , wherein a drain region of said MOSFET of the second conductivity type and said second diffusion region of the first conductivity type are formed, adjacent to each other, in said well region of the first conductivity type.
6. The semiconductor integrated circuit device according to claim 1 , further comprising:
a first diffusion region of the second conductivity type formed in said well of the second conductivity type, said first diffusion region of the second conductivity type being connected to a second back bias supplying power supply line that supplies a back bias to be supplied to said well region of the second conductivity type; and
a MOSFET of the first conductivity type formed in said well region of the second conductivity type, a gate and a drain of said MOSFET of the first conductivity type being connected to said well region of the second conductivity type through a second diffusion region of the second conductivity type formed in the well region which is not connected to the second back bias supplying power supply line, and a source of said MOSFET of the first conductivity type being connected to said second power supply line.
7. The semiconductor integrated circuit device according to claim 6 , wherein a plurality of said first diffusion regions of the second conductivity type are present in said well region of the second conductivity type, and the second diffusion region of the second conductivity type is arranged generally in the middle of two of said first diffusion regions of the second conductivity type, said second diffusion region of the second conductivity type serving as a connecting spot between the drain of said MOSFET of the first conductivity type and said well region of the second conductivity type.
8. The semiconductor integrated circuit device according to claim 7 , wherein a drain region of said MOSFET of the first conductivity type and said second diffusion region of the second conductivity type are formed, adjacent to each other, in said well region of the second conductivity type.
9. The semiconductor integrated circuit device according to claim 6 , further comprising:
a plurality of cells each formed over said well region of the first conductivity type and said well region of the second conductivity type;
at least one portion of each of said cells including said MOSFET of the first conductivity type, the second diffusion region of the second conductivity type, said MOSFET of the second conductivity type, and a second diffusion region of the first conductivity type;
said second diffusion region of the second conductivity type serving as a connecting point between the drain of said MOSFET of the first conductivity type and said well region of the second conductivity type;
said second diffusion region of the first conductivity type serving as a connecting spot between the drain of said MOSFET of the second conductivity type and said well region of the first conductivity type.
10. The semiconductor integrated circuit device according to claim 9 , wherein a drain region of said MOSFET of the first conductivity type and said second diffusion region of the second conductivity type are formed, adjacent to each other, in said well region of the second conductivity type.