Data processing apparatus for controlling access to a memory based upon detection of completion of a DMA bus cycle

1. A data processing apparatus, comprising:

a first bus connected to a first memory;

a first Central Processing Unit (CPU) being accessible to the first memory via the first bus;

a first Direct Memory Access (DMA) controller being accessible to the first memory via the first bus; and

a monitor circuit connected to the first bus and monitoring addresses transferred on the first bus,

wherein the addresses transferred on the first bus are transmitted from the first DMA controller to the first memory via the first bus, and

wherein the first CPU accesses the first memory based on monitoring results by the monitor circuit, the monitoring results indicating whether a DMA transfer controlled by the first DMA controller has been completed.

2. The data processing apparatus according to claim 1 ,

wherein the monitor circuit outputs a first permit signal when a monitor target address is transferred on the first bus, thereby indicating a completion of the DMA transfer, and

the first CPU accesses the first memory in response to the first permit signal.

3. The data processing apparatus according to claim 2 , wherein the monitor circuit comprises:

a first target address register storing the monitor target address;

an address acquisition circuit acquiring the addresses transferred on the first bus;

a comparator comparing the address stored in the first target address register with the address acquired by the acquisition circuit; and

a first permit signal output circuit outputting the first permit signal when the address acquired by the acquisition circuit matches the address stored in the first target address register.

4. The data processing apparatus according to claim 3 , wherein the monitor circuit further comprises:

a check register storing comparison results by the comparator, and

wherein the comparator updates the check register when the address acquired by the acquisition circuit matches the address stored in the first target address register, and

the first permit signal output circuit outputs the first permit signal in response to the updating of the check register.

5. The data processing apparatus according to claim 3 , further comprising:

a second DMA controller being accessible to the first memory via the first bus, and

wherein the monitor circuit further comprises:

a second target address register storing the monitor target address linked to the second DMA controller, and

wherein the first target address register stores the monitor target address linked to the first DMA controller, and

wherein the first permit signal output circuit outputting the first permit signal when the address acquired by the acquisition circuit matches the address stored in the second target address register.

6. The data processing apparatus according to claim 3 , further comprising:

a second CPU being accessible to the first memory via the first bus, and

wherein the monitor circuit further comprises:

a second target address register storing the monitor target address linked to the second CPU; and

a second permit signal output circuit outputting the second permit signal when the address acquired by the acquisition circuit matches the address stored in the second target address register, and

wherein the first target address register stores the monitor target address linked to the first CPU, and

wherein the second CPU accesses the first memory in response to the second permit signal.

7. The data processing apparatus according to claim 2 ,

wherein the first CPU accesses a storage region of the first memory corresponding to the addresses transferred on the first bus in response to the first permit signal.

8. The data processing apparatus according to claim 2 ,

wherein the first CPU accesses the first memory according to either the first permit signal or a second permit signal output from the first DMA controller.

9. The data processing apparatus according to claim 2 , further comprising:

an interrupt selector unit receiving the first permit signal and a second permit signal output from the first DMA controller and selecting either the first permit signal and the second permit signal according to a select signal output from the first CPU, and

wherein the first CPU accesses the first memory based on a selection result by the interrupt selector unit.

10. A data processing apparatus, comprising:

a first bus connected to a first memory;

a first Central Processing Unit (CPU) being accessible to the first memory via the first bus;

a first Direct Memory Access (DMA) controller being accessible to the first memory via the first bus;

a second bus connected between the first bus and the first DMA controller; and

a monitor circuit connected to the first bus and monitoring addresses transferred on the first bus,

wherein the addresses transferred on the first bus are transmitted from the first DMA controller to the first memory via the first bus,

wherein the first CPU accesses the first memory based on monitoring results by the monitor circuit, and

wherein the monitor circuit monitors addresses output from the first DMA controller to the first bus via the second bus.

11. The data processing apparatus according to claim 10 ,

wherein the second bus is connected to a second memory, and

the first DMA controller reads data stored in the second memory and transfers the read data to the first memory via the first bus and the second bus.

12. The data processing apparatus according to claim 11 , further comprising:

a bus bridge connected between the first bus and the second bus,

wherein the bus bridge includes a buffer to store the read data temporarily.

13. A data processing apparatus, comprising:

a first bus;

a Direct Memory Access (DMA) controller coupled to the first bus and operative to perform a DMA bus cycle on the first bus;

a Central Processing Unit (CPU) coupled to the first bus and operative to perform a CPU bus cycle on the first bus; and

a monitor circuit coupled to the first bus and temporarily storing target address information to produce access information indicating that address information appearing on the first bus based on the DMA bus cycle is equal to the target address information, thereby signifying that the DMA bus cycle has been completed, the CPU being granted to perform the CPU bus cycle when the access information is produced.

14. The data processing apparatus according to claim 13 , wherein the monitor circuit comprises:

a permit signal output circuit outputting a permit signal to the CPU when the access information is produced, and

wherein the CPU being granted to perform the CPU bus cycle based on the permit signal.

15. The data processing apparatus according to claim 14 , wherein the monitor circuit further comprises:

a check register storing the access information, and

wherein the permit signal output circuit outputting the permit signal in response to a update of the check register.

16. The data processing apparatus according to claim 13 , wherein the monitor circuit comprises:

a target address register storing the target address information;

a address acquisition circuit acquiring the address information appearing on the first bus; and

a comparator producing the access information.

17. The data processing apparatus according to claim 13 , further comprising:

a second bus coupled between the first bus and the DMA controller, and

wherein the address information appearing on the first bus is output from the DMA controller to the first bus via the second bus.

18. The data processing apparatus according to claim 17 , further comprising:

a bus bridge coupled between the first bus and the second bus, and

wherein the bus bridge temporarily stores data transferred from the second bus to the first bus.

19. The data processing apparatus according to claim 13 ,

wherein the first bus is coupled to a memory, and

wherein the address information appearing on the first bus is transmitted from the DMA controller to the memory.

20. The data processing apparatus according to claim 19 ,

wherein the CPU executes the bus cycle to access a storage region of the memory corresponding to the address information appearing on the first bus when the access information is produced.