Semiconductor device
The semiconductor device 1 includes a substrate 3 , a semiconductor chip 4 mounted on the substrate 3 , the substrate 3 , a bump 5 connecting the substrate 3 and the semiconductor chip 4 , and an underfill 6 filling in around the bump 5 . In the case of a bump 5 composed of a high-melting-point solder having a melting point of 230° C. or more, the underfill 6 is composed of a resin material having an elastic modulus in the range of 30 MPa to 3000 MPa. In the case of a bump 5 composed of a lead-free solder, the underfill 6 is composed of a resin material having an elastic modulus in the range of 150 MPa to 800 MPa. An insulating layer 311 of buildup layers 31 of the substrate 3 has a linear expansion coefficient of 35 ppm/° C. or less in the in-plane direction of the substrate at temperatures in the range of 25° C. to the glass transition temperature.
1. A semiconductor device comprising:
a substrate;
a semiconductor element mounted on the substrate;
a bump connecting the substrate and the semiconductor element; and
an underfill filling in around the bump, wherein
the bump comprises a high-melting-point solder, the high melting point solder having a melting point of 230° C. or more,
the underfill comprises a resin material, the resin material having an elastic modulus in the range of 30 MPa to 510 MPa,
the substrate has a buildup layer which includes resin-containing insulating layers and conductive interconnection layers, with the insulating layers and conductive interconnection layers being alternately laminated, and each of the conductive interconnection layers being connected by conductive layers, the conductive layers being formed in via holes, the via holes being formed in the insulating layers,
a linear expansion coefficient of at least one of the resin-containing insulating layers of the buildup layer in an in-plane direction of the substrate at temperatures between 25° C. and the glass transition temperature of the at least one insulating layer is 35 ppm/° C. or less, and
the difference in linear expansion coefficient between the underfill and the bump at temperatures between 25° C. and the glass transition temperature of the at least one insulating layer is 10 ppm/° C. or less.
2. The semiconductor device according to claim 1 , wherein the semiconductor element comprises a silicon substrate; an interlayer insulating film provided on the silicon substrate, the interlayer insulating film comprising a low-dielectric layer having a relative permittivity of 3.3 or less; and a lead provided in the interlayer insulating film.
3. The semiconductor device according to claim 2 , wherein the difference in linear expansion coefficient between the underfill and the at least one insulating layer of the buildup layer at temperatures between 25° C. and the glass transition temperature of the at least one insulating layer is 25 ppm/° C. or less.
4. The semiconductor device according to claim 1 , wherein the difference in linear expansion coefficient between the underfill and the at least one insulating layer of the buildup layer at temperatures between 25° C. and the glass transition temperature of the at least one insulating layer is 25 ppm/° C. or less.
5. The semiconductor device according to claim 1 , wherein
the substrate has a core layer having another insulating layer in which a through hole is formed, and
a conductive layer which is provided inside said through hole, and wherein
said conductive layer is connected to one of the conductive interconnection layers of the buildup layer.
6. The semiconductor device according to claim 1 , wherein the resin of the at least one insulating layer of the buildup layer comprises a cyanate resin.
7. The semiconductor device according to claim 6 , wherein the cyanate resin is a novolak cyanate resin.
8. A semiconductor device comprising:
a substrate;
a semiconductor element mounted on the substrate;
a bump connecting the substrate and the semiconductor element; and
an underfill filling in around the bump, wherein
the bump comprises a lead-free solder,
the underfill comprises a resin material, the resin material having an elastic modulus in the range of 150 MPa to 800 MPa,
the substrate has a buildup layer which includes resin-containing insulating layers and conductive interconnection layers, with the insulating layers and conductive interconnection layers being alternately laminated, and the conductive interconnection layers being connected by conductive layers, the conductive layers being formed in via holes, the via holes being formed in the insulating layers,
a linear expansion coefficient of at least one of the resin-containing insulating layers of the buildup layer in an in-plane direction of the substrate at temperatures between 25° C. and the glass transition temperature of the at least one insulating layer is 35 ppm/° C. or less the difference in linear expansion coefficient between the underfill and the bump at temperatures between 25° C. and the glass transition temperature of the at least one insulating layer is 10 ppm/° C. or less.
9. The semiconductor device according to claim 8 , wherein the semiconductor element comprises a silicon substrate; an interlayer insulating film provided on the silicon substrate, the interlayer insulating film comprising a low-dielectric layer having a relative permittivity of 3.3 or less; and a lead provided in the interlayer insulating film.
10. The semiconductor device according to claim 9 , wherein the difference in linear expansion coefficient between the underfill and the at least one insulating layer of the buildup layer at temperatures between 25° C. and the glass transition temperature of the at least one insulating layer is 25 ppm/° C. or less.
11. The semiconductor device according to claim 8 , wherein the difference in linear expansion coefficient between the underfill and the at least one insulating layer of the buildup layer at temperatures between 25° C. and the glass transition temperature of the at least one insulating layer is 25 ppm/° C. or less.
12. The semiconductor device according to claim 8 , wherein the substrate has a core layer having another insulating layer in which a through hole is formed, and
a conductive layer which is provided inside said through hole, and wherein
said conductive layer is connected to one of the conductive interconnection layers of the buildup layer.
13. The semiconductor device according to claim 8 , wherein the resin of the at least one insulating layer of the buildup layer comprises a cyanate resin.
14. The semiconductor device according to claim 13 , wherein the cyanate resin is a novolak cyanate resin.