IP Library Granted Patent US 7,575,944
Granted Patent B2
US 7,575,944 · App. 11/889,392 · Granted Aug 18, 2009

Method of manufacturing nitride-based semiconductor light emitting diode

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Quick Facts
Patent No.
US 7,575,944
App. No.
11/889,392
Granted
Aug 18, 2009
Kind
B2
Abstract

Provided is a method of manufacturing a nitride-based semiconductor LED including sequentially forming an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer on a substrate; forming a Pd/Zn alloy layer on the p-type nitride semiconductor layer; heat-treating the p-type nitride semiconductor layer on which the Pd/Zn alloy layer is formed; removing the Pd/Zn alloy layer formed on the p-type nitride semiconductor layer; mesa-etching portions of the p-type nitride semiconductor layer, the active layer, and the n-type nitride semiconductor layer such that a portion of the upper surface of the n-type nitride semiconductor layer is exposed; and forming an n-electrode and a p-electrode on the exposed n-type nitride semiconductor layer and the p-type nitride semiconductor layer, respectively.

Claims (37)

1. A method of manufacturing a nitride-based semiconductor light emitting diode (LED), the method comprising:

sequentially forming an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer on a substrate;

forming a Pd/Zn alloy layer on the p-type nitride semiconductor layer;

heat-treating the p-type nitride semiconductor layer on which the Pd/Zn alloy layer is formed;

removing the Pd/Zn alloy layer formed on the p-type nitride semiconductor layer;

mesa-etching portions of the p-type nitride semiconductor layer, the active layer, and the n-type nitride semiconductor layer such that a portion of the upper surface of the n-type nitride semiconductor layer is exposed; and

forming an n-electrode and a p-electrode on the exposed n-type nitride semiconductor layer and the p-type nitride semiconductor layer, respectively.

2. The method according to claim 1 ,

wherein the Pd/Zn alloy layer is formed on the p-type nitride semiconductor layer excluding the region where the p-electrode is formed.

3. The method according to claim 1 ,

wherein the removing of the Pd/Zn alloy layer is performed in such a manner that the concentration of Pd and Zn remaining in the p-type nitride semiconductor layer is maintained at 1×10 16 to 1×10 20 cm −3 , through the heat-treating of the p-type nitride semiconductor layer.

4. The method according to claim 3 ,

wherein Pd and Zn remaining in the p-type nitride semiconductor layer are positioned in the range of 2 to 100 nm from the upper surface of the p-type nitride semiconductor layer.

5. The method according to claim 1 ,

wherein the removing of the Pd/Zn alloy layer is performed in such a manner that the surface roughness of the p-type nitride semiconductor layer coming in contact with the Pd/Zn alloy layer is maintained at 0.5 to 10 nm.

6. The method according to claim 1 further comprising:

forming a transparent electrode layer on the p-type nitride semiconductor layer, after the removing of the Pd/Zn alloy layer.

7. The method according to claim 6 ,

wherein the transparent electrode layer is formed of a mixture obtained by adding one or more elements, selected from the group consisting of Sn, Zn, Mg, Cu, Ag, and Al, into indium oxide.

8. A method of manufacturing a nitride-based semiconductor LED, the method comprising:

sequentially forming an n-type nitride semiconductor layer, an active layer, and a p-type nitride semiconductor layer on a substrate;

forming a Pd/Zn alloy layer on the p-type nitride semiconductor layer;

heat-treating the p-type nitride semiconductor layer on which the Pd/Zn alloy layer is formed;

mesa-etching portions of the Pd/Zn alloy layer, the p-type nitride semiconductor layer, the active layer, and the n-type nitride semiconductor layer such that a portion of the upper surface of the n-type nitride semiconductor layer is exposed; and

forming an n-electrode and a p-electrode on the exposed n-type nitride semiconductor layer and the p-type nitride semiconductor layer, respectively.

9. The method according to claim 8 ,

wherein the Pd/Zn alloy layer is formed on the p-type nitride semiconductor layer excluding the region where the p-electrode is formed.

10. The method according to claim 8 ,

wherein the heat-treating of the p-type nitride semiconductor layer is performed in such a manner that the concentration of Pd and Zn remaining in the p-type nitride semiconductor layer is maintained at 1×10 16 to 1×10 20 cm −3 .

11. The method according to claim 10 ,

wherein Pd and Zn remaining in the p-type nitride semiconductor layer are positioned in the range of 2 to 100 nm from the upper surface of the p-type nitride semiconductor layer.

12. The method according to claim 8 ,

wherein the heat-treating of the p-type nitride semiconductor layer is performed in such a manner that the surface roughness of the p-type nitride semiconductor layer coming in contact with the Pd/Zn alloy layer is maintained at 0.5 to 10 nm.

13. The method according to claim 8 further comprising:

forming a transparent electrode layer on the p-type nitride semiconductor layer, before the forming of the n-electrode and the p-electrode.

14. The method according to claim 13 ,

wherein the transparent electrode layer is formed of a mixture obtained by adding one or more elements, selected from the group consisting of Sn, Zn, Mg, Cu, Ag, and Al, into indium oxide.

Assignments (3)
MERGER Recorded Aug 7, 2012
From: SAMSUNG LED CO., LTD.
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 028744/0272 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2010
From: SAMSUNG ELECTRO-MECHANICS CO., LTD.
To: SAMSUNG LED CO., LTD.
Reel/Frame 024375/0448 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2007
From: KIM, SUN WOON; PARK, SEONG JU; KIM, JA YEON; KWON, MIN KI; LEE, DONG JU; HAN, JAE HO
To: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Reel/Frame 019745/0092 →